1Marvell Berlin SoC Family Device Tree Bindings
2---------------------------------------------------------------
3
4Boards with a SoC of the Marvell Berlin family, e.g. Armada 1500
5shall have the following properties:
6
7* Required root node properties:
8compatible: must contain "marvell,berlin"
9
10In addition, the above compatible shall be extended with the specific
11SoC and board used. Currently known SoC compatibles are:
12    "marvell,berlin2"      for Marvell Armada 1500 (BG2, 88DE3100),
13    "marvell,berlin2cd"    for Marvell Armada 1500-mini (BG2CD, 88DE3005)
14    "marvell,berlin2ct"    for Marvell Armada ? (BG2CT, 88DE????)
15    "marvell,berlin2q"     for Marvell Armada 1500-pro (BG2Q, 88DE3114)
16    "marvell,berlin3"      for Marvell Armada ? (BG3, 88DE????)
17
18* Example:
19
20/ {
21	model = "Sony NSZ-GS7";
22	compatible = "sony,nsz-gs7", "marvell,berlin2", "marvell,berlin";
23
24	...
25}
26
27* Marvell Berlin CPU control bindings
28
29CPU control register allows various operations on CPUs, like resetting them
30independently.
31
32Required properties:
33- compatible: should be "marvell,berlin-cpu-ctrl"
34- reg: address and length of the register set
35
36Example:
37
38cpu-ctrl@f7dd0000 {
39	compatible = "marvell,berlin-cpu-ctrl";
40	reg = <0xf7dd0000 0x10000>;
41};
42
43* Marvell Berlin2 chip control binding
44
45Marvell Berlin SoCs have a chip control register set providing several
46individual registers dealing with pinmux, padmux, clock, reset, and secondary
47CPU boot address. Unfortunately, the individual registers are spread among the
48chip control registers, so there should be a single DT node only providing the
49different functions which are described below.
50
51Required properties:
52- compatible: shall be one of
53	"marvell,berlin2-chip-ctrl" for BG2
54	"marvell,berlin2cd-chip-ctrl" for BG2CD
55	"marvell,berlin2q-chip-ctrl" for BG2Q
56- reg: address and length of following register sets for
57  BG2/BG2CD: chip control register set
58  BG2Q: chip control register set and cpu pll registers
59
60* Marvell Berlin2 system control binding
61
62Marvell Berlin SoCs have a system control register set providing several
63individual registers dealing with pinmux, padmux, and reset.
64
65Required properties:
66- compatible: should be one of
67	"marvell,berlin2-system-ctrl" for BG2
68	"marvell,berlin2cd-system-ctrl" for BG2CD
69	"marvell,berlin2q-system-ctrl" for BG2Q
70- reg: address and length of the system control register set
71
72* Clock provider binding
73
74As clock related registers are spread among the chip control registers, the
75chip control node also provides the clocks. Marvell Berlin2 (BG2, BG2CD, BG2Q)
76SoCs share the same IP for PLLs and clocks, with some minor differences in
77features and register layout.
78
79Required properties:
80- #clock-cells: shall be set to 1
81- clocks: clock specifiers referencing the core clock input clocks
82- clock-names: array of strings describing the input clock specifiers above.
83    Allowed clock-names for the reference clocks are
84      "refclk" for the SoCs osciallator input on all SoCs,
85    and SoC-specific input clocks for
86      BG2/BG2CD: "video_ext0" for the external video clock input
87
88Clocks provided by core clocks shall be referenced by a clock specifier
89indexing one of the provided clocks. Refer to dt-bindings/clock/berlin<soc>.h
90for the corresponding index mapping.
91
92* Pin controller binding
93
94Pin control registers are part of both register sets, chip control and system
95control. The pins controlled are organized in groups, so no actual pin
96information is needed.
97
98A pin-controller node should contain subnodes representing the pin group
99configurations, one per function. Each subnode has the group name and the muxing
100function used.
101
102Be aware the Marvell Berlin datasheets use the keyword 'mode' for what is called
103a 'function' in the pin-controller subsystem.
104
105Required subnode-properties:
106- groups: a list of strings describing the group names.
107- function: a string describing the function used to mux the groups.
108
109* Reset controller binding
110
111A reset controller is part of the chip control registers set. The chip control
112node also provides the reset. The register set is not at the same offset between
113Berlin SoCs.
114
115Required property:
116- #reset-cells: must be set to 2
117
118Example:
119
120chip: chip-control@ea0000 {
121	compatible = "marvell,berlin2-chip-ctrl";
122	#clock-cells = <1>;
123	#reset-cells = <2>;
124	reg = <0xea0000 0x400>;
125	clocks = <&refclk>, <&externaldev 0>;
126	clock-names = "refclk", "video_ext0";
127
128	spi1_pmux: spi1-pmux {
129		groups = "G0";
130		function = "spi1";
131	};
132};
133
134sysctrl: system-controller@d000 {
135	compatible = "marvell,berlin2-system-ctrl";
136	reg = <0xd000 0x100>;
137
138	uart0_pmux: uart0-pmux {
139		groups = "GSM4";
140		function = "uart0";
141	};
142
143	uart1_pmux: uart1-pmux {
144		groups = "GSM5";
145		function = "uart1";
146	};
147
148	uart2_pmux: uart2-pmux {
149		groups = "GSM3";
150		function = "uart2";
151	};
152};
153