1* ARM Generic Interrupt Controller
2
3ARM SMP cores are often associated with a GIC, providing per processor
4interrupts (PPI), shared processor interrupts (SPI) and software
5generated interrupts (SGI).
6
7Primary GIC is attached directly to the CPU and typically has PPIs and SGIs.
8Secondary GICs are cascaded into the upward interrupt controller and do not
9have PPIs or SGIs.
10
11Main node required properties:
12
13- compatible : should be one of:
14	"arm,gic-400"
15	"arm,cortex-a15-gic"
16	"arm,cortex-a9-gic"
17	"arm,cortex-a7-gic"
18	"arm,arm11mp-gic"
19	"brcm,brahma-b15-gic"
20	"arm,arm1176jzf-devchip-gic"
21	"qcom,msm-8660-qgic"
22	"qcom,msm-qgic2"
23- interrupt-controller : Identifies the node as an interrupt controller
24- #interrupt-cells : Specifies the number of cells needed to encode an
25  interrupt source.  The type shall be a <u32> and the value shall be 3.
26
27  The 1st cell is the interrupt type; 0 for SPI interrupts, 1 for PPI
28  interrupts.
29
30  The 2nd cell contains the interrupt number for the interrupt type.
31  SPI interrupts are in the range [0-987].  PPI interrupts are in the
32  range [0-15].
33
34  The 3rd cell is the flags, encoded as follows:
35	bits[3:0] trigger type and level flags.
36		1 = low-to-high edge triggered
37		2 = high-to-low edge triggered (invalid for SPIs)
38		4 = active high level-sensitive
39		8 = active low level-sensitive (invalid for SPIs).
40	bits[15:8] PPI interrupt cpu mask.  Each bit corresponds to each of
41	the 8 possible cpus attached to the GIC.  A bit set to '1' indicated
42	the interrupt is wired to that CPU.  Only valid for PPI interrupts.
43	Also note that the configurability of PPI interrupts is IMPLEMENTATION
44	DEFINED and as such not guaranteed to be present (most SoC available
45	in 2014 seem to ignore the setting of this flag and use the hardware
46	default value).
47
48- reg : Specifies base physical address(s) and size of the GIC registers. The
49  first region is the GIC distributor register base and size. The 2nd region is
50  the GIC cpu interface register base and size.
51
52Optional
53- interrupts	: Interrupt source of the parent interrupt controller on
54  secondary GICs, or VGIC maintenance interrupt on primary GIC (see
55  below).
56
57- cpu-offset	: per-cpu offset within the distributor and cpu interface
58  regions, used when the GIC doesn't have banked registers. The offset is
59  cpu-offset * cpu-nr.
60
61Example:
62
63	intc: interrupt-controller@fff11000 {
64		compatible = "arm,cortex-a9-gic";
65		#interrupt-cells = <3>;
66		#address-cells = <1>;
67		interrupt-controller;
68		reg = <0xfff11000 0x1000>,
69		      <0xfff10100 0x100>;
70	};
71
72
73* GIC virtualization extensions (VGIC)
74
75For ARM cores that support the virtualization extensions, additional
76properties must be described (they only exist if the GIC is the
77primary interrupt controller).
78
79Required properties:
80
81- reg : Additional regions specifying the base physical address and
82  size of the VGIC registers. The first additional region is the GIC
83  virtual interface control register base and size. The 2nd additional
84  region is the GIC virtual cpu interface register base and size.
85
86- interrupts : VGIC maintenance interrupt.
87
88Example:
89
90	interrupt-controller@2c001000 {
91		compatible = "arm,cortex-a15-gic";
92		#interrupt-cells = <3>;
93		interrupt-controller;
94		reg = <0x2c001000 0x1000>,
95		      <0x2c002000 0x1000>,
96		      <0x2c004000 0x2000>,
97		      <0x2c006000 0x2000>;
98		interrupts = <1 9 0xf04>;
99	};
100
101
102* GICv2m extension for MSI/MSI-x support (Optional)
103
104Certain revisions of GIC-400 supports MSI/MSI-x via V2M register frame(s).
105This is enabled by specifying v2m sub-node(s).
106
107Required properties:
108
109- compatible	    : The value here should contain "arm,gic-v2m-frame".
110
111- msi-controller    : Identifies the node as an MSI controller.
112
113- reg		    : GICv2m MSI interface register base and size
114
115Optional properties:
116
117- arm,msi-base-spi  : When the MSI_TYPER register contains an incorrect
118  		      value, this property should contain the SPI base of
119		      the MSI frame, overriding the HW value.
120
121- arm,msi-num-spis  : When the MSI_TYPER register contains an incorrect
122  		      value, this property should contain the number of
123		      SPIs assigned to the frame, overriding the HW value.
124
125Example:
126
127	interrupt-controller@e1101000 {
128		compatible = "arm,gic-400";
129		#interrupt-cells = <3>;
130		#address-cells = <2>;
131		#size-cells = <2>;
132		interrupt-controller;
133		interrupts = <1 8 0xf04>;
134		ranges = <0 0 0 0xe1100000 0 0x100000>;
135		reg = <0x0 0xe1110000 0 0x01000>,
136		      <0x0 0xe112f000 0 0x02000>,
137		      <0x0 0xe1140000 0 0x10000>,
138		      <0x0 0xe1160000 0 0x10000>;
139		v2m0: v2m@0x8000 {
140			compatible = "arm,gic-v2m-frame";
141			msi-controller;
142			reg = <0x0 0x80000 0 0x1000>;
143		};
144
145		....
146
147		v2mN: v2m@0x9000 {
148			compatible = "arm,gic-v2m-frame";
149			msi-controller;
150			reg = <0x0 0x90000 0 0x1000>;
151		};
152	};
153