1* Samsung Exynos Power Domains 2 3Exynos processors include support for multiple power domains which are used 4to gate power to one or more peripherals on the processor. 5 6Required Properties: 7- compatible: should be one of the following. 8 * samsung,exynos4210-pd - for exynos4210 type power domain. 9- reg: physical base address of the controller and length of memory mapped 10 region. 11- #power-domain-cells: number of cells in power domain specifier; 12 must be 0. 13 14Optional Properties: 15- clocks: List of clock handles. The parent clocks of the input clocks to the 16 devices in this power domain are set to oscclk before power gating 17 and restored back after powering on a domain. This is required for 18 all domains which are powered on and off and not required for unused 19 domains. 20- clock-names: The following clocks can be specified: 21 - oscclk: Oscillator clock. 22 - pclkN, clkN: Pairs of parent of input clock and input clock to the 23 devices in this power domain. Maximum of 4 pairs (N = 0 to 3) 24 are supported currently. 25 - asbN: Clocks required by asynchronous bridges (ASB) present in 26 the power domain. These clock should be enabled during power 27 domain on/off operations. 28- power-domains: phandle pointing to the parent power domain, for more details 29 see Documentation/devicetree/bindings/power/power_domain.txt 30 31Node of a device using power domains must have a power-domains property 32defined with a phandle to respective power domain. 33 34Example: 35 36 lcd0: power-domain-lcd0 { 37 compatible = "samsung,exynos4210-pd"; 38 reg = <0x10023C00 0x10>; 39 #power-domain-cells = <0>; 40 }; 41 42 mfc_pd: power-domain@10044060 { 43 compatible = "samsung,exynos4210-pd"; 44 reg = <0x10044060 0x20>; 45 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MOUT_SW_ACLK333>, 46 <&clock CLK_MOUT_USER_ACLK333>; 47 clock-names = "oscclk", "pclk0", "clk0"; 48 #power-domain-cells = <0>; 49 }; 50 51See Documentation/devicetree/bindings/power/power_domain.txt for description 52of consumer-side bindings. 53