1<html><head><meta http-equiv="Content-Type" content="text/html; charset=ANSI_X3.4-1968"><title>EH recovery actions</title><meta name="generator" content="DocBook XSL Stylesheets V1.78.1"><link rel="home" href="index.html" title="libATA Developer's Guide"><link rel="up" href="ataExceptions.html" title="Chapter 7. ATA errors and exceptions"><link rel="prev" href="ataExceptions.html" title="Chapter 7. ATA errors and exceptions"><link rel="next" href="PiixInt.html" title="Chapter 8. ata_piix Internals"></head><body bgcolor="white" text="black" link="#0000FF" vlink="#840084" alink="#0000FF"><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">EH recovery actions</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="ataExceptions.html">Prev</a> </td><th width="60%" align="center">Chapter 7. ATA errors and exceptions</th><td width="20%" align="right"> <a accesskey="n" href="PiixInt.html">Next</a></td></tr></table><hr></div><div class="sect1"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a name="exrec"></a>EH recovery actions</h2></div></div></div><div class="toc"><dl class="toc"><dt><span class="sect2"><a href="exrec.html#exrecClr">Clearing error condition</a></span></dt><dt><span class="sect2"><a href="exrec.html#exrecRst">Reset</a></span></dt><dt><span class="sect2"><a href="exrec.html#exrecReconf">Reconfigure transport</a></span></dt></dl></div><p> 2 This section discusses several important recovery actions. 3 </p><div class="sect2"><div class="titlepage"><div><div><h3 class="title"><a name="exrecClr"></a>Clearing error condition</h3></div></div></div><p> 4 Many controllers require its error registers to be cleared by 5 error handler. Different controllers may have different 6 requirements. 7 </p><p> 8 For SATA, it's strongly recommended to clear at least SError 9 register during error handling. 10 </p></div><div class="sect2"><div class="titlepage"><div><div><h3 class="title"><a name="exrecRst"></a>Reset</h3></div></div></div><p> 11 During EH, resetting is necessary in the following cases. 12 </p><div class="itemizedlist"><ul class="itemizedlist" style="list-style-type: disc; "><li class="listitem"><p> 13 HSM is in unknown or invalid state 14 </p></li><li class="listitem"><p> 15 HBA is in unknown or invalid state 16 </p></li><li class="listitem"><p> 17 EH needs to make HBA/device forget about in-flight commands 18 </p></li><li class="listitem"><p> 19 HBA/device behaves weirdly 20 </p></li></ul></div><p> 21 Resetting during EH might be a good idea regardless of error 22 condition to improve EH robustness. Whether to reset both or 23 either one of HBA and device depends on situation but the 24 following scheme is recommended. 25 </p><div class="itemizedlist"><ul class="itemizedlist" style="list-style-type: disc; "><li class="listitem"><p> 26 When it's known that HBA is in ready state but ATA/ATAPI 27 device is in unknown state, reset only device. 28 </p></li><li class="listitem"><p> 29 If HBA is in unknown state, reset both HBA and device. 30 </p></li></ul></div><p> 31 HBA resetting is implementation specific. For a controller 32 complying to taskfile/BMDMA PCI IDE, stopping active DMA 33 transaction may be sufficient iff BMDMA state is the only HBA 34 context. But even mostly taskfile/BMDMA PCI IDE complying 35 controllers may have implementation specific requirements and 36 mechanism to reset themselves. This must be addressed by 37 specific drivers. 38 </p><p> 39 OTOH, ATA/ATAPI standard describes in detail ways to reset 40 ATA/ATAPI devices. 41 </p><div class="variablelist"><dl class="variablelist"><dt><span class="term">PATA hardware reset</span></dt><dd><p> 42 This is hardware initiated device reset signalled with 43 asserted PATA RESET- signal. There is no standard way to 44 initiate hardware reset from software although some 45 hardware provides registers that allow driver to directly 46 tweak the RESET- signal. 47 </p></dd><dt><span class="term">Software reset</span></dt><dd><p> 48 This is achieved by turning CONTROL SRST bit on for at 49 least 5us. Both PATA and SATA support it but, in case of 50 SATA, this may require controller-specific support as the 51 second Register FIS to clear SRST should be transmitted 52 while BSY bit is still set. Note that on PATA, this resets 53 both master and slave devices on a channel. 54 </p></dd><dt><span class="term">EXECUTE DEVICE DIAGNOSTIC command</span></dt><dd><p> 55 Although ATA/ATAPI standard doesn't describe exactly, EDD 56 implies some level of resetting, possibly similar level 57 with software reset. Host-side EDD protocol can be handled 58 with normal command processing and most SATA controllers 59 should be able to handle EDD's just like other commands. 60 As in software reset, EDD affects both devices on a PATA 61 bus. 62 </p><p> 63 Although EDD does reset devices, this doesn't suit error 64 handling as EDD cannot be issued while BSY is set and it's 65 unclear how it will act when device is in unknown/weird 66 state. 67 </p></dd><dt><span class="term">ATAPI DEVICE RESET command</span></dt><dd><p> 68 This is very similar to software reset except that reset 69 can be restricted to the selected device without affecting 70 the other device sharing the cable. 71 </p></dd><dt><span class="term">SATA phy reset</span></dt><dd><p> 72 This is the preferred way of resetting a SATA device. In 73 effect, it's identical to PATA hardware reset. Note that 74 this can be done with the standard SCR Control register. 75 As such, it's usually easier to implement than software 76 reset. 77 </p></dd></dl></div><p> 78 One more thing to consider when resetting devices is that 79 resetting clears certain configuration parameters and they 80 need to be set to their previous or newly adjusted values 81 after reset. 82 </p><p> 83 Parameters affected are. 84 </p><div class="itemizedlist"><ul class="itemizedlist" style="list-style-type: disc; "><li class="listitem"><p> 85 CHS set up with INITIALIZE DEVICE PARAMETERS (seldom used) 86 </p></li><li class="listitem"><p> 87 Parameters set with SET FEATURES including transfer mode setting 88 </p></li><li class="listitem"><p> 89 Block count set with SET MULTIPLE MODE 90 </p></li><li class="listitem"><p> 91 Other parameters (SET MAX, MEDIA LOCK...) 92 </p></li></ul></div><p> 93 ATA/ATAPI standard specifies that some parameters must be 94 maintained across hardware or software reset, but doesn't 95 strictly specify all of them. Always reconfiguring needed 96 parameters after reset is required for robustness. Note that 97 this also applies when resuming from deep sleep (power-off). 98 </p><p> 99 Also, ATA/ATAPI standard requires that IDENTIFY DEVICE / 100 IDENTIFY PACKET DEVICE is issued after any configuration 101 parameter is updated or a hardware reset and the result used 102 for further operation. OS driver is required to implement 103 revalidation mechanism to support this. 104 </p></div><div class="sect2"><div class="titlepage"><div><div><h3 class="title"><a name="exrecReconf"></a>Reconfigure transport</h3></div></div></div><p> 105 For both PATA and SATA, a lot of corners are cut for cheap 106 connectors, cables or controllers and it's quite common to see 107 high transmission error rate. This can be mitigated by 108 lowering transmission speed. 109 </p><p> 110 The following is a possible scheme Jeff Garzik suggested. 111 </p><div class="blockquote"><blockquote class="blockquote"><p> 112 If more than $N (3?) transmission errors happen in 15 minutes, 113 </p><div class="itemizedlist"><ul class="itemizedlist" style="list-style-type: disc; "><li class="listitem"><p> 114 if SATA, decrease SATA PHY speed. if speed cannot be decreased, 115 </p></li><li class="listitem"><p> 116 decrease UDMA xfer speed. if at UDMA0, switch to PIO4, 117 </p></li><li class="listitem"><p> 118 decrease PIO xfer speed. if at PIO3, complain, but continue 119 </p></li></ul></div></blockquote></div></div></div><div class="navfooter"><hr><table width="100%" summary="Navigation footer"><tr><td width="40%" align="left"><a accesskey="p" href="ataExceptions.html">Prev</a> </td><td width="20%" align="center"><a accesskey="u" href="ataExceptions.html">Up</a></td><td width="40%" align="right"> <a accesskey="n" href="PiixInt.html">Next</a></td></tr><tr><td width="40%" align="left" valign="top">Chapter 7. ATA errors and exceptions </td><td width="20%" align="center"><a accesskey="h" href="index.html">Home</a></td><td width="40%" align="right" valign="top"> Chapter 8. ata_piix Internals</td></tr></table></div></body></html> 120