1<html><head><meta http-equiv="Content-Type" content="text/html; charset=ANSI_X3.4-1968"><title>enum irq_gc_flags</title><meta name="generator" content="DocBook XSL Stylesheets V1.78.1"><link rel="home" href="index.html" title="Linux generic IRQ handling"><link rel="up" href="structs.html" title="Chapter&#160;8.&#160;Structures"><link rel="prev" href="API-struct-irq-chip-generic.html" title="struct irq_chip_generic"><link rel="next" href="API-struct-irqaction.html" title="struct irqaction"></head><body bgcolor="white" text="black" link="#0000FF" vlink="#840084" alink="#0000FF"><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center"><span class="phrase">enum irq_gc_flags</span></th></tr><tr><td width="20%" align="left"><a accesskey="p" href="API-struct-irq-chip-generic.html">Prev</a>&#160;</td><th width="60%" align="center">Chapter&#160;8.&#160;Structures</th><td width="20%" align="right">&#160;<a accesskey="n" href="API-struct-irqaction.html">Next</a></td></tr></table><hr></div><div class="refentry"><a name="API-enum-irq-gc-flags"></a><div class="titlepage"></div><div class="refnamediv"><h2>Name</h2><p>enum irq_gc_flags &#8212; 
2     Initialization flags for generic irq chips
3 </p></div><div class="refsynopsisdiv"><h2>Synopsis</h2><pre class="programlisting">
4enum irq_gc_flags {
5  IRQ_GC_INIT_MASK_CACHE,
6  IRQ_GC_INIT_NESTED_LOCK,
7  IRQ_GC_MASK_CACHE_PER_TYPE,
8  IRQ_GC_NO_MASK,
9  IRQ_GC_BE_IO
10};  </pre></div><div class="refsect1"><a name="idp1103041852"></a><h2>Constants</h2><div class="variablelist"><dl class="variablelist"><dt><span class="term">IRQ_GC_INIT_MASK_CACHE</span></dt><dd><p>
11   Initialize the mask_cache by reading mask reg
12      </p></dd><dt><span class="term">IRQ_GC_INIT_NESTED_LOCK</span></dt><dd><p>
13   Set the lock class of the irqs to nested for
14   irq chips which need to call <code class="function">irq_set_wake</code> on
15   the parent irq. Usually GPIO implementations
16      </p></dd><dt><span class="term">IRQ_GC_MASK_CACHE_PER_TYPE</span></dt><dd><p>
17   Mask cache is chip type private
18      </p></dd><dt><span class="term">IRQ_GC_NO_MASK</span></dt><dd><p>
19   Do not calculate irq_data-&gt;mask
20      </p></dd><dt><span class="term">IRQ_GC_BE_IO</span></dt><dd><p>
21   Use big-endian register accesses (default: LE)
22      </p></dd></dl></div></div></div><div class="navfooter"><hr><table width="100%" summary="Navigation footer"><tr><td width="40%" align="left"><a accesskey="p" href="API-struct-irq-chip-generic.html">Prev</a>&#160;</td><td width="20%" align="center"><a accesskey="u" href="structs.html">Up</a></td><td width="40%" align="right">&#160;<a accesskey="n" href="API-struct-irqaction.html">Next</a></td></tr><tr><td width="40%" align="left" valign="top"><span class="phrase">struct irq_chip_generic</span>&#160;</td><td width="20%" align="center"><a accesskey="h" href="index.html">Home</a></td><td width="40%" align="right" valign="top">&#160;<span class="phrase">struct irqaction</span></td></tr></table></div></body></html>
23