Searched refs:wrpll (Results 1 – 5 of 5) sorted by relevance
946 u32 wrpll; in hsw_ddi_calc_wrpll_link() local948 wrpll = I915_READ(reg); in hsw_ddi_calc_wrpll_link()949 switch (wrpll & WRPLL_PLL_REF_MASK) { in hsw_ddi_calc_wrpll_link()967 r = wrpll & WRPLL_DIVIDER_REF_MASK; in hsw_ddi_calc_wrpll_link()968 p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT; in hsw_ddi_calc_wrpll_link()969 n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT; in hsw_ddi_calc_wrpll_link()1287 crtc_state->dpll_hw_state.wrpll = val; in hsw_ddi_pll_select()2464 I915_WRITE(WRPLL_CTL(pll->id), pll->config.hw_state.wrpll); in hsw_ddi_wrpll_enable()2507 hw_state->wrpll = val; in hsw_ddi_wrpll_get_hw_state()
265 pipe_config->dpll_hw_state.wrpll = 0; in intel_crt_compute_config()
372 uint32_t wrpll; member
3092 seq_printf(m, " wrpll: 0x%08x\n", pll->config.hw_state.wrpll); in i915_shared_dplls_info()
12087 pipe_config->dpll_hw_state.wrpll, in intel_dump_pipe_config()12613 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll); in intel_pipe_config_compare()