Searched refs:uart1_mux (Results 1 - 10 of 10) sorted by relevance

/linux-4.4.14/drivers/clk/mmp/
H A Dclk-of-pxa168.c132 {0, "uart1_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART1, 4, 3, 0, &uart1_lock},
154 {PXA168_CLK_UART1, "uart1_clk", "uart1_mux", CLK_SET_RATE_PARENT, APBC_UART1, 0x3, 0x3, 0x0, 0, &uart1_lock},
H A Dclk-of-pxa1928.c101 {0, "uart1_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, PXA1928_CLK_UART1 * 4, 4, 3, 0, &uart1_lock},
124 {PXA1928_CLK_UART1, "uart1_clk", "uart1_mux", CLK_SET_RATE_PARENT, PXA1928_CLK_UART1 * 4, 0x3, 0x3, 0x0, 0, &uart1_lock},
H A Dclk-of-pxa910.c130 {0, "uart1_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART1, 4, 3, 0, &uart1_lock},
152 {PXA910_CLK_UART1, "uart1_clk", "uart1_mux", CLK_SET_RATE_PARENT, APBC_UART1, 0x3, 0x3, 0x0, 0, &uart1_lock},
H A Dclk-pxa168.c213 clk = clk_register_mux(NULL, "uart1_mux", uart_parent, pxa168_clk_init()
220 clk = mmp_clk_register_apbc("uart1", "uart1_mux", pxa168_clk_init()
H A Dclk-pxa910.c218 clk = clk_register_mux(NULL, "uart1_mux", uart_parent, pxa910_clk_init()
225 clk = mmp_clk_register_apbc("uart1", "uart1_mux", pxa910_clk_init()
H A Dclk-mmp2.c260 clk = clk_register_mux(NULL, "uart1_mux", uart_parent, mmp2_clk_init()
267 clk = mmp_clk_register_apbc("uart1", "uart1_mux", mmp2_clk_init()
H A Dclk-of-mmp2.c143 {0, "uart1_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART1, 4, 3, 0, &uart1_lock},
169 {MMP2_CLK_UART1, "uart1_clk", "uart1_mux", CLK_SET_RATE_PARENT, APBC_UART1, 0x7, 0x3, 0x0, 0, &uart1_lock},
/linux-4.4.14/drivers/pinctrl/
H A Dpinctrl-adi2-bf54x.c317 static const unsigned short uart1_mux[] = { variable
485 ADI_PIN_GROUP("uart1grp", uart1_pins, uart1_mux),
H A Dpinctrl-adi2-bf60x.c272 static const unsigned short uart1_mux[] = { variable
421 ADI_PIN_GROUP("uart1grp", uart1_pins, uart1_mux),
/linux-4.4.14/drivers/clk/hisilicon/
H A Dclk-hi3620.c111 { HI3620_UART1_MUX, "uart1_mux", uart1_mux_p, ARRAY_SIZE(uart1_mux_p), CLK_SET_RATE_PARENT, 0x100, 8, 1, CLK_MUX_HIWORD_MASK, },
187 { HI3620_UARTCLK1, "uartclk1", "uart1_mux", CLK_SET_RATE_PARENT, 0x40, 17, 0, },

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