Searched refs:uart0_mux (Results 1 - 10 of 10) sorted by relevance

/linux-4.4.14/drivers/clk/mmp/
H A Dclk-of-pxa168.c131 {0, "uart0_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART0, 4, 3, 0, &uart0_lock},
153 {PXA168_CLK_UART0, "uart0_clk", "uart0_mux", CLK_SET_RATE_PARENT, APBC_UART0, 0x3, 0x3, 0x0, 0, &uart0_lock},
H A Dclk-of-pxa1928.c100 {0, "uart0_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, PXA1928_CLK_UART0 * 4, 4, 3, 0, &uart0_lock},
123 {PXA1928_CLK_UART0, "uart0_clk", "uart0_mux", CLK_SET_RATE_PARENT, PXA1928_CLK_UART0 * 4, 0x3, 0x3, 0x0, 0, &uart0_lock},
H A Dclk-of-pxa910.c129 {0, "uart0_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART0, 4, 3, 0, &uart0_lock},
151 {PXA910_CLK_UART0, "uart0_clk", "uart0_mux", CLK_SET_RATE_PARENT, APBC_UART0, 0x3, 0x3, 0x0, 0, &uart0_lock},
H A Dclk-pxa168.c202 clk = clk_register_mux(NULL, "uart0_mux", uart_parent, pxa168_clk_init()
209 clk = mmp_clk_register_apbc("uart0", "uart0_mux", pxa168_clk_init()
H A Dclk-pxa910.c207 clk = clk_register_mux(NULL, "uart0_mux", uart_parent, pxa910_clk_init()
214 clk = mmp_clk_register_apbc("uart0", "uart0_mux", pxa910_clk_init()
H A Dclk-mmp2.c249 clk = clk_register_mux(NULL, "uart0_mux", uart_parent, mmp2_clk_init()
256 clk = mmp_clk_register_apbc("uart0", "uart0_mux", mmp2_clk_init()
H A Dclk-of-mmp2.c142 {0, "uart0_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART0, 4, 3, 0, &uart0_lock},
168 {MMP2_CLK_UART0, "uart0_clk", "uart0_mux", CLK_SET_RATE_PARENT, APBC_UART0, 0x7, 0x3, 0x0, 0, &uart0_lock},
/linux-4.4.14/drivers/pinctrl/
H A Dpinctrl-adi2-bf54x.c312 static const unsigned short uart0_mux[] = { variable
484 ADI_PIN_GROUP("uart0grp", uart0_pins, uart0_mux),
H A Dpinctrl-adi2-bf60x.c262 static const unsigned short uart0_mux[] = { variable
419 ADI_PIN_GROUP("uart0grp", uart0_pins, uart0_mux),
/linux-4.4.14/drivers/clk/hisilicon/
H A Dclk-hi3620.c110 { HI3620_UART0_MUX, "uart0_mux", uart0_mux_p, ARRAY_SIZE(uart0_mux_p), CLK_SET_RATE_PARENT, 0x100, 7, 1, CLK_MUX_HIWORD_MASK, },
186 { HI3620_UARTCLK0, "uartclk0", "uart0_mux", CLK_SET_RATE_PARENT, 0x40, 16, 0, },

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