Searched refs:post_div_table (Results 1 - 4 of 4) sorted by relevance
| /linux-4.4.14/drivers/clk/imx/ |
| H A D | clk-imx6q.c | 101 static struct clk_div_table post_div_table[] = { variable in typeref:struct:clk_div_table
161 post_div_table[1].div = 1; imx6q_clocks_init()
162 post_div_table[2].div = 1; imx6q_clocks_init()
272 clk[IMX6QDL_CLK_PLL4_POST_DIV] = clk_register_divider_table(NULL, "pll4_post_div", "pll4_audio", CLK_SET_RATE_PARENT, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock); imx6q_clocks_init()
274 clk[IMX6QDL_CLK_PLL5_POST_DIV] = clk_register_divider_table(NULL, "pll5_post_div", "pll5_video", CLK_SET_RATE_PARENT, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock); imx6q_clocks_init()
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| H A D | clk-imx6sl.c | 82 static struct clk_div_table post_div_table[] = { variable in typeref:struct:clk_div_table
271 clks[IMX6SL_CLK_PLL4_POST_DIV] = clk_register_divider_table(NULL, "pll4_post_div", "pll4_audio", CLK_SET_RATE_PARENT, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock); imx6sl_clocks_init()
273 clks[IMX6SL_CLK_PLL5_POST_DIV] = clk_register_divider_table(NULL, "pll5_post_div", "pll5_video", CLK_SET_RATE_PARENT, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock); imx6sl_clocks_init()
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| H A D | clk-imx6ul.c | 85 static struct clk_div_table post_div_table[] = { variable in typeref:struct:clk_div_table
203 CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock); imx6ul_clocks_init()
207 CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock); imx6ul_clocks_init()
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| H A D | clk-imx6sx.c | 116 static struct clk_div_table post_div_table[] = { variable in typeref:struct:clk_div_table
261 CLK_SET_RATE_PARENT, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock); imx6sx_clocks_init()
265 CLK_SET_RATE_PARENT, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock); imx6sx_clocks_init()
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