/linux-4.4.14/drivers/ata/ |
H A D | libahci.c | 262 void __iomem *port_mmio = ahci_port_base(ap); ahci_show_port_cmd() local 264 return sprintf(buf, "%x\n", readl(port_mmio + PORT_CMD)); ahci_show_port_cmd() 558 void __iomem *port_mmio = ahci_port_base(link->ap); ahci_scr_read() local 562 *val = readl(port_mmio + offset); ahci_scr_read() 570 void __iomem *port_mmio = ahci_port_base(link->ap); ahci_scr_write() local 574 writel(val, port_mmio + offset); ahci_scr_write() 582 void __iomem *port_mmio = ahci_port_base(ap); ahci_start_engine() local 586 tmp = readl(port_mmio + PORT_CMD); ahci_start_engine() 588 writel(tmp, port_mmio + PORT_CMD); ahci_start_engine() 589 readl(port_mmio + PORT_CMD); /* flush */ ahci_start_engine() 595 void __iomem *port_mmio = ahci_port_base(ap); ahci_stop_engine() local 598 tmp = readl(port_mmio + PORT_CMD); ahci_stop_engine() 606 writel(tmp, port_mmio + PORT_CMD); ahci_stop_engine() 609 tmp = ata_wait_register(ap, port_mmio + PORT_CMD, ahci_stop_engine() 620 void __iomem *port_mmio = ahci_port_base(ap); ahci_start_fis_rx() local 628 port_mmio + PORT_LST_ADDR_HI); ahci_start_fis_rx() 629 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR); ahci_start_fis_rx() 633 port_mmio + PORT_FIS_ADDR_HI); ahci_start_fis_rx() 634 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR); ahci_start_fis_rx() 637 tmp = readl(port_mmio + PORT_CMD); ahci_start_fis_rx() 639 writel(tmp, port_mmio + PORT_CMD); ahci_start_fis_rx() 642 readl(port_mmio + PORT_CMD); ahci_start_fis_rx() 648 void __iomem *port_mmio = ahci_port_base(ap); ahci_stop_fis_rx() local 652 tmp = readl(port_mmio + PORT_CMD); ahci_stop_fis_rx() 654 writel(tmp, port_mmio + PORT_CMD); ahci_stop_fis_rx() 657 tmp = ata_wait_register(ap, port_mmio + PORT_CMD, PORT_CMD_FIS_ON, ahci_stop_fis_rx() 668 void __iomem *port_mmio = ahci_port_base(ap); ahci_power_up() local 671 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK; ahci_power_up() 676 writel(cmd, port_mmio + PORT_CMD); ahci_power_up() 680 writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD); ahci_power_up() 689 void __iomem *port_mmio = ahci_port_base(ap); ahci_set_lpm() local 698 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); ahci_set_lpm() 704 u32 cmd = readl(port_mmio + PORT_CMD); ahci_set_lpm() 710 writel(cmd, port_mmio + PORT_CMD); ahci_set_lpm() 711 readl(port_mmio + PORT_CMD); ahci_set_lpm() 721 writel(cmd, port_mmio + PORT_CMD); ahci_set_lpm() 740 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); ahci_set_lpm() 750 void __iomem *port_mmio = ahci_port_base(ap); ahci_power_down() local 757 scontrol = readl(port_mmio + PORT_SCR_CTL); ahci_power_down() 759 writel(scontrol, port_mmio + PORT_SCR_CTL); ahci_power_down() 762 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK; ahci_power_down() 764 writel(cmd, port_mmio + PORT_CMD); ahci_power_down() 1119 void __iomem *port_mmio) ahci_port_init() 1132 tmp = readl(port_mmio + PORT_SCR_ERR); ahci_port_init() 1134 writel(tmp, port_mmio + PORT_SCR_ERR); ahci_port_init() 1137 tmp = readl(port_mmio + PORT_IRQ_STAT); ahci_port_init() 1140 writel(tmp, port_mmio + PORT_IRQ_STAT); ahci_port_init() 1145 tmp = readl(port_mmio + PORT_CMD); ahci_port_init() 1155 void __iomem *port_mmio; ahci_init_controller() local 1161 port_mmio = ahci_port_base(ap); ahci_init_controller() 1165 ahci_port_init(host->dev, ap, i, mmio, port_mmio); ahci_init_controller() 1189 void __iomem *port_mmio = ahci_port_base(ap); ahci_dev_classify() local 1193 tmp = readl(port_mmio + PORT_SIG); ahci_dev_classify() 1219 void __iomem *port_mmio = ahci_port_base(ap); ahci_kick_engine() local 1221 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF; ahci_kick_engine() 1245 tmp = readl(port_mmio + PORT_CMD); ahci_kick_engine() 1247 writel(tmp, port_mmio + PORT_CMD); ahci_kick_engine() 1250 tmp = ata_wait_register(ap, port_mmio + PORT_CMD, ahci_kick_engine() 1268 void __iomem *port_mmio = ahci_port_base(ap); ahci_exec_polled_cmd() local 1278 tmp = readl(port_mmio + PORT_FBS); ahci_exec_polled_cmd() 1281 writel(tmp, port_mmio + PORT_FBS); ahci_exec_polled_cmd() 1286 writel(1, port_mmio + PORT_CMD_ISSUE); ahci_exec_polled_cmd() 1289 tmp = ata_wait_register(ap, port_mmio + PORT_CMD_ISSUE, ahci_exec_polled_cmd() 1296 readl(port_mmio + PORT_CMD_ISSUE); /* flush */ ahci_exec_polled_cmd() 1385 void __iomem *port_mmio = ahci_port_base(link->ap); ahci_check_ready() local 1386 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF; ahci_check_ready() 1405 void __iomem *port_mmio = ahci_port_base(link->ap); ahci_bad_pmp_check_ready() local 1406 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF; ahci_bad_pmp_check_ready() 1407 u32 irq_status = readl(port_mmio + PORT_IRQ_STAT); ahci_bad_pmp_check_ready() 1423 void __iomem *port_mmio = ahci_port_base(ap); ahci_pmp_retry_softreset() local 1439 irq_sts = readl(port_mmio + PORT_IRQ_STAT); ahci_pmp_retry_softreset() 1488 void __iomem *port_mmio = ahci_port_base(ap); ahci_postreset() local 1494 new_tmp = tmp = readl(port_mmio + PORT_CMD); ahci_postreset() 1500 writel(new_tmp, port_mmio + PORT_CMD); ahci_postreset() 1501 readl(port_mmio + PORT_CMD); /* flush */ ahci_postreset() 1580 void __iomem *port_mmio = ahci_port_base(ap); ahci_fbs_dec_intr() local 1581 u32 fbs = readl(port_mmio + PORT_FBS); ahci_fbs_dec_intr() 1590 writel(fbs | PORT_FBS_DEC, port_mmio + PORT_FBS); ahci_fbs_dec_intr() 1591 fbs = readl(port_mmio + PORT_FBS); ahci_fbs_dec_intr() 1594 fbs = readl(port_mmio + PORT_FBS); ahci_fbs_dec_intr() 1614 void __iomem *port_mmio = ahci_port_base(ap); ahci_error_intr() local 1615 u32 fbs = readl(port_mmio + PORT_FBS); ahci_error_intr() 1713 void __iomem *port_mmio, u32 status) ahci_handle_port_interrupt() 1774 qc_active = readl(port_mmio + PORT_SCR_ACT); ahci_handle_port_interrupt() 1775 qc_active |= readl(port_mmio + PORT_CMD_ISSUE); ahci_handle_port_interrupt() 1780 qc_active = readl(port_mmio + PORT_SCR_ACT); ahci_handle_port_interrupt() 1782 qc_active = readl(port_mmio + PORT_CMD_ISSUE); ahci_handle_port_interrupt() 1798 void __iomem *port_mmio = ahci_port_base(ap); ahci_port_intr() local 1801 status = readl(port_mmio + PORT_IRQ_STAT); ahci_port_intr() 1802 writel(status, port_mmio + PORT_IRQ_STAT); ahci_port_intr() 1804 ahci_handle_port_interrupt(ap, port_mmio, status); ahci_port_intr() 1811 void __iomem *port_mmio = ahci_port_base(ap); ahci_port_thread_fn() local 1819 ahci_handle_port_interrupt(ap, port_mmio, status); ahci_port_thread_fn() 1828 void __iomem *port_mmio = ahci_port_base(ap); ahci_multi_irqs_intr() local 1834 status = readl(port_mmio + PORT_IRQ_STAT); ahci_multi_irqs_intr() 1835 writel(status, port_mmio + PORT_IRQ_STAT); ahci_multi_irqs_intr() 1953 void __iomem *port_mmio = ahci_port_base(ap); ahci_qc_issue() local 1963 writel(1 << qc->tag, port_mmio + PORT_SCR_ACT); ahci_qc_issue() 1966 u32 fbs = readl(port_mmio + PORT_FBS); ahci_qc_issue() 1969 writel(fbs, port_mmio + PORT_FBS); ahci_qc_issue() 1973 writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE); ahci_qc_issue() 2007 void __iomem *port_mmio = ahci_port_base(ap); ahci_freeze() local 2010 writel(0, port_mmio + PORT_IRQ_MASK); ahci_freeze() 2017 void __iomem *port_mmio = ahci_port_base(ap); ahci_thaw() local 2022 tmp = readl(port_mmio + PORT_IRQ_STAT); ahci_thaw() 2023 writel(tmp, port_mmio + PORT_IRQ_STAT); ahci_thaw() 2027 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); ahci_thaw() 2059 void __iomem *port_mmio = ahci_port_base(ap); ahci_set_aggressive_devslp() local 2065 devslp = readl(port_mmio + PORT_DEVSLP); ahci_set_aggressive_devslp() 2075 port_mmio + PORT_DEVSLP); ahci_set_aggressive_devslp() 2120 writel(devslp, port_mmio + PORT_DEVSLP); ahci_set_aggressive_devslp() 2136 void __iomem *port_mmio = ahci_port_base(ap); ahci_enable_fbs() local 2143 fbs = readl(port_mmio + PORT_FBS); ahci_enable_fbs() 2154 writel(fbs | PORT_FBS_EN, port_mmio + PORT_FBS); ahci_enable_fbs() 2155 fbs = readl(port_mmio + PORT_FBS); ahci_enable_fbs() 2170 void __iomem *port_mmio = ahci_port_base(ap); ahci_disable_fbs() local 2177 fbs = readl(port_mmio + PORT_FBS); ahci_disable_fbs() 2187 writel(fbs & ~PORT_FBS_EN, port_mmio + PORT_FBS); ahci_disable_fbs() 2188 fbs = readl(port_mmio + PORT_FBS); ahci_disable_fbs() 2201 void __iomem *port_mmio = ahci_port_base(ap); ahci_pmp_attach() local 2205 cmd = readl(port_mmio + PORT_CMD); ahci_pmp_attach() 2207 writel(cmd, port_mmio + PORT_CMD); ahci_pmp_attach() 2222 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); ahci_pmp_attach() 2227 void __iomem *port_mmio = ahci_port_base(ap); ahci_pmp_detach() local 2233 cmd = readl(port_mmio + PORT_CMD); ahci_pmp_detach() 2235 writel(cmd, port_mmio + PORT_CMD); ahci_pmp_detach() 2241 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); ahci_pmp_detach() 2301 void __iomem *port_mmio = ahci_port_base(ap); ahci_port_start() local 2302 u32 cmd = readl(port_mmio + PORT_CMD); ahci_port_start() 1117 ahci_port_init(struct device *dev, struct ata_port *ap, int port_no, void __iomem *mmio, void __iomem *port_mmio) ahci_port_init() argument 1712 ahci_handle_port_interrupt(struct ata_port *ap, void __iomem *port_mmio, u32 status) ahci_handle_port_interrupt() argument
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H A D | sata_mv.c | 650 static int mv_stop_edma_engine(void __iomem *port_mmio); 957 void __iomem *port_mmio = mv_ap_base(ap); mv_save_cached_regs() local 960 pp->cached.fiscfg = readl(port_mmio + FISCFG); mv_save_cached_regs() 961 pp->cached.ltmode = readl(port_mmio + LTMODE); mv_save_cached_regs() 962 pp->cached.haltcond = readl(port_mmio + EDMA_HALTCOND); mv_save_cached_regs() 963 pp->cached.unknown_rsvd = readl(port_mmio + EDMA_UNKNOWN_RSVD); mv_save_cached_regs() 1001 static void mv_set_edma_ptrs(void __iomem *port_mmio, mv_set_edma_ptrs() argument 1014 writel((pp->crqb_dma >> 16) >> 16, port_mmio + EDMA_REQ_Q_BASE_HI); mv_set_edma_ptrs() 1016 port_mmio + EDMA_REQ_Q_IN_PTR); mv_set_edma_ptrs() 1017 writelfl(index, port_mmio + EDMA_REQ_Q_OUT_PTR); mv_set_edma_ptrs() 1026 writel((pp->crpb_dma >> 16) >> 16, port_mmio + EDMA_RSP_Q_BASE_HI); mv_set_edma_ptrs() 1027 writelfl(index, port_mmio + EDMA_RSP_Q_IN_PTR); mv_set_edma_ptrs() 1029 port_mmio + EDMA_RSP_Q_OUT_PTR); mv_set_edma_ptrs() 1077 void __iomem *port_mmio, mv_clear_and_enable_port_irqs() 1087 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE); mv_clear_and_enable_port_irqs() 1095 writelfl(0, port_mmio + FIS_IRQ_CAUSE); mv_clear_and_enable_port_irqs() 1173 static void mv_start_edma(struct ata_port *ap, void __iomem *port_mmio, mv_start_edma() argument 1188 mv_set_edma_ptrs(port_mmio, hpriv, pp); mv_start_edma() 1189 mv_clear_and_enable_port_irqs(ap, port_mmio, DONE_IRQ|ERR_IRQ); mv_start_edma() 1191 writelfl(EDMA_EN, port_mmio + EDMA_CMD); mv_start_edma() 1198 void __iomem *port_mmio = mv_ap_base(ap); mv_wait_for_edma_empty_idle() local 1211 u32 edma_stat = readl(port_mmio + EDMA_STATUS); mv_wait_for_edma_empty_idle() 1221 * @port_mmio: io base address 1226 static int mv_stop_edma_engine(void __iomem *port_mmio) mv_stop_edma_engine() argument 1231 writelfl(EDMA_DS, port_mmio + EDMA_CMD); mv_stop_edma_engine() 1235 u32 reg = readl(port_mmio + EDMA_CMD); mv_stop_edma_engine() 1245 void __iomem *port_mmio = mv_ap_base(ap); mv_stop_edma() local 1253 if (mv_stop_edma_engine(port_mmio)) { mv_stop_edma() 1494 void __iomem *port_mmio; mv_config_fbs() local 1514 port_mmio = mv_ap_base(ap); mv_config_fbs() 1515 mv_write_cached_reg(port_mmio + FISCFG, old_fiscfg, fiscfg); mv_config_fbs() 1516 mv_write_cached_reg(port_mmio + LTMODE, old_ltmode, ltmode); mv_config_fbs() 1517 mv_write_cached_reg(port_mmio + EDMA_HALTCOND, old_haltcond, haltcond); mv_config_fbs() 1619 void __iomem *port_mmio = mv_ap_base(ap); mv_edma_cfg() local 1675 writelfl(cfg, port_mmio + EDMA_CFG); mv_edma_cfg() 1899 void __iomem *port_mmio = mv_ap_base(ap); mv_bmdma_setup() local 1905 writel(0, port_mmio + BMDMA_CMD); mv_bmdma_setup() 1909 port_mmio + BMDMA_PRD_HIGH); mv_bmdma_setup() 1911 port_mmio + BMDMA_PRD_LOW); mv_bmdma_setup() 1927 void __iomem *port_mmio = mv_ap_base(ap); mv_bmdma_start() local 1932 writelfl(cmd, port_mmio + BMDMA_CMD); mv_bmdma_start() 1946 void __iomem *port_mmio = mv_ap_base(ap); mv_bmdma_stop_ap() local 1950 cmd = readl(port_mmio + BMDMA_CMD); mv_bmdma_stop_ap() 1953 writelfl(cmd, port_mmio + BMDMA_CMD); mv_bmdma_stop_ap() 1976 void __iomem *port_mmio = mv_ap_base(ap); mv_bmdma_status() local 1983 reg = readl(port_mmio + BMDMA_STATUS); mv_bmdma_status() 2242 void __iomem *port_mmio = mv_ap_base(ap); mv_send_fis() local 2247 old_ifctl = readl(port_mmio + SATA_IFCTL); mv_send_fis() 2249 writelfl(ifctl, port_mmio + SATA_IFCTL); mv_send_fis() 2253 writel(fis[i], port_mmio + VENDOR_UNIQUE_FIS); mv_send_fis() 2256 writelfl(ifctl | 0x200, port_mmio + SATA_IFCTL); mv_send_fis() 2257 writelfl(fis[final_word], port_mmio + VENDOR_UNIQUE_FIS); mv_send_fis() 2264 ifstat = readl(port_mmio + SATA_IFSTAT); mv_send_fis() 2268 writelfl(old_ifctl, port_mmio + SATA_IFCTL); mv_send_fis() 2349 void __iomem *port_mmio = mv_ap_base(ap); mv_qc_issue() local 2365 mv_start_edma(ap, port_mmio, pp, qc->tf.protocol); mv_qc_issue() 2371 port_mmio + EDMA_REQ_Q_IN_PTR); mv_qc_issue() 2476 void __iomem *port_mmio = mv_ap_base(ap); mv_get_err_pmp_map() local 2478 return readl(port_mmio + SATA_TESTCTL) >> 16; mv_get_err_pmp_map() 2508 void __iomem *port_mmio = mv_ap_base(ap); mv_req_q_empty() local 2511 in_ptr = (readl(port_mmio + EDMA_REQ_Q_IN_PTR) mv_req_q_empty() 2513 out_ptr = (readl(port_mmio + EDMA_REQ_Q_OUT_PTR) mv_req_q_empty() 2653 void __iomem *port_mmio = mv_ap_base(ap); mv_err_intr() local 2671 edma_err_cause = readl(port_mmio + EDMA_ERR_IRQ_CAUSE); mv_err_intr() 2673 fis_cause = readl(port_mmio + FIS_IRQ_CAUSE); mv_err_intr() 2674 writelfl(~fis_cause, port_mmio + FIS_IRQ_CAUSE); mv_err_intr() 2676 writelfl(~edma_err_cause, port_mmio + EDMA_ERR_IRQ_CAUSE); mv_err_intr() 2816 void __iomem *port_mmio = mv_ap_base(ap); mv_process_crpb_entries() local 2824 in_index = (readl(port_mmio + EDMA_RSP_Q_IN_PTR) mv_process_crpb_entries() 2852 port_mmio + EDMA_RSP_Q_OUT_PTR); mv_process_crpb_entries() 3172 #define ZERO(reg) writel(0, port_mmio + (reg)) mv5_reset_hc_port() 3176 void __iomem *port_mmio = mv_port_base(mmio, port); mv5_reset_hc_port() local 3181 writel(0x11f, port_mmio + EDMA_CFG); mv5_reset_hc_port() 3192 writel(0xbc, port_mmio + EDMA_IORDY_TMOUT); mv5_reset_hc_port() 3334 void __iomem *port_mmio; mv6_read_preamp() local 3344 port_mmio = mv_port_base(mmio, idx); mv6_read_preamp() 3345 tmp = readl(port_mmio + PHY_MODE2); mv6_read_preamp() 3359 void __iomem *port_mmio = mv_port_base(mmio, port); mv6_phy_errata() local 3369 m2 = readl(port_mmio + PHY_MODE2); mv6_phy_errata() 3372 writel(m2, port_mmio + PHY_MODE2); mv6_phy_errata() 3376 m2 = readl(port_mmio + PHY_MODE2); mv6_phy_errata() 3378 writel(m2, port_mmio + PHY_MODE2); mv6_phy_errata() 3387 m3 = readl(port_mmio + PHY_MODE3); mv6_phy_errata() 3395 u32 m4 = readl(port_mmio + PHY_MODE4); mv6_phy_errata() 3405 writel(m4, port_mmio + PHY_MODE4); mv6_phy_errata() 3413 writel(m3, port_mmio + PHY_MODE3); mv6_phy_errata() 3416 m2 = readl(port_mmio + PHY_MODE2); mv6_phy_errata() 3429 writel(m2, port_mmio + PHY_MODE2); mv6_phy_errata() 3443 void __iomem *port_mmio; mv_soc_read_preamp() local 3446 port_mmio = mv_port_base(mmio, idx); mv_soc_read_preamp() 3447 tmp = readl(port_mmio + PHY_MODE2); mv_soc_read_preamp() 3454 #define ZERO(reg) writel(0, port_mmio + (reg)) mv_soc_reset_hc_port() 3458 void __iomem *port_mmio = mv_port_base(mmio, port); mv_soc_reset_hc_port() local 3463 writel(0x101f, port_mmio + EDMA_CFG); mv_soc_reset_hc_port() 3474 writel(0x800, port_mmio + EDMA_IORDY_TMOUT); mv_soc_reset_hc_port() 3520 void __iomem *port_mmio = mv_port_base(mmio, port); mv_soc_65n_phy_errata() local 3523 reg = readl(port_mmio + PHY_MODE3); mv_soc_65n_phy_errata() 3528 writel(reg, port_mmio + PHY_MODE3); mv_soc_65n_phy_errata() 3530 reg = readl(port_mmio + PHY_MODE4); mv_soc_65n_phy_errata() 3533 writel(reg, port_mmio + PHY_MODE4); mv_soc_65n_phy_errata() 3535 reg = readl(port_mmio + PHY_MODE9_GEN2); mv_soc_65n_phy_errata() 3539 writel(reg, port_mmio + PHY_MODE9_GEN2); mv_soc_65n_phy_errata() 3541 reg = readl(port_mmio + PHY_MODE9_GEN1); mv_soc_65n_phy_errata() 3545 writel(reg, port_mmio + PHY_MODE9_GEN1); mv_soc_65n_phy_errata() 3564 static void mv_setup_ifcfg(void __iomem *port_mmio, int want_gen2i) mv_setup_ifcfg() argument 3566 u32 ifcfg = readl(port_mmio + SATA_IFCFG); mv_setup_ifcfg() 3571 writelfl(ifcfg, port_mmio + SATA_IFCFG); mv_setup_ifcfg() 3577 void __iomem *port_mmio = mv_port_base(mmio, port_no); mv_reset_channel() local 3584 mv_stop_edma_engine(port_mmio); mv_reset_channel() 3585 writelfl(EDMA_RESET, port_mmio + EDMA_CMD); mv_reset_channel() 3589 mv_setup_ifcfg(port_mmio, 1); mv_reset_channel() 3596 writelfl(EDMA_RESET, port_mmio + EDMA_CMD); mv_reset_channel() 3598 writelfl(0, port_mmio + EDMA_CMD); mv_reset_channel() 3609 void __iomem *port_mmio = mv_ap_base(ap); mv_pmp_select() local 3610 u32 reg = readl(port_mmio + SATA_IFCTL); mv_pmp_select() 3615 writelfl(reg, port_mmio + SATA_IFCTL); mv_pmp_select() 3686 void __iomem *port_mmio = mv_ap_base(ap); mv_eh_thaw() local 3690 writel(0, port_mmio + EDMA_ERR_IRQ_CAUSE); mv_eh_thaw() 3702 * @port_mmio: base address of the port 3711 static void mv_port_init(struct ata_ioports *port, void __iomem *port_mmio) mv_port_init() argument 3713 void __iomem *serr, *shd_base = port_mmio + SHD_BLK; mv_port_init() 3731 serr = port_mmio + mv_scr_offset(SCR_ERROR); mv_port_init() 3733 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE); mv_port_init() 3736 writelfl(~EDMA_ERR_IRQ_TRANSIENT, port_mmio + EDMA_ERR_IRQ_MASK); mv_port_init() 3739 readl(port_mmio + EDMA_CFG), mv_port_init() 3740 readl(port_mmio + EDMA_ERR_IRQ_CAUSE), mv_port_init() 3741 readl(port_mmio + EDMA_ERR_IRQ_MASK)); mv_port_init() 3978 void __iomem *port_mmio = mv_port_base(mmio, port); mv_init_host() local 3980 mv_port_init(&ap->ioaddr, port_mmio); mv_init_host() 4444 void __iomem *port_mmio = mv_port_base(hpriv->base, port); mv_pci_init_one() local 4445 unsigned int offset = port_mmio - hpriv->base; mv_pci_init_one() 1076 mv_clear_and_enable_port_irqs(struct ata_port *ap, void __iomem *port_mmio, unsigned int port_irqs) mv_clear_and_enable_port_irqs() argument
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H A D | ahci_xgene.c | 155 void __iomem *port_mmio = ahci_port_base(ap); xgene_ahci_restart_engine() local 164 if (xgene_ahci_poll_reg_val(ap, port_mmio + xgene_ahci_restart_engine() 176 fbs = readl(port_mmio + PORT_FBS); xgene_ahci_restart_engine() 177 writel(fbs | PORT_FBS_EN, port_mmio + PORT_FBS); xgene_ahci_restart_engine() 178 fbs = readl(port_mmio + PORT_FBS); xgene_ahci_restart_engine() 209 void *port_mmio = ahci_port_base(ap); xgene_ahci_qc_issue() local 216 port_fbs = readl(port_mmio + PORT_FBS); xgene_ahci_qc_issue() 219 writel(port_fbs, port_mmio + PORT_FBS); xgene_ahci_qc_issue() 372 void __iomem *port_mmio = ahci_port_base(ap); xgene_ahci_do_hardreset() local 386 val = readl(port_mmio + PORT_SCR_ERR); xgene_ahci_do_hardreset() 397 val = readl(port_mmio + PORT_SCR_ERR); xgene_ahci_do_hardreset() 398 writel(val, port_mmio + PORT_SCR_ERR); xgene_ahci_do_hardreset() 408 void __iomem *port_mmio = ahci_port_base(ap); xgene_ahci_hardreset() local 418 portcmd_saved = readl(port_mmio + PORT_CMD); xgene_ahci_hardreset() 419 portclb_saved = readl(port_mmio + PORT_LST_ADDR); xgene_ahci_hardreset() 420 portclbhi_saved = readl(port_mmio + PORT_LST_ADDR_HI); xgene_ahci_hardreset() 421 portrxfis_saved = readl(port_mmio + PORT_FIS_ADDR); xgene_ahci_hardreset() 422 portrxfishi_saved = readl(port_mmio + PORT_FIS_ADDR_HI); xgene_ahci_hardreset() 429 writel(portcmd_saved, port_mmio + PORT_CMD); xgene_ahci_hardreset() 430 writel(portclb_saved, port_mmio + PORT_LST_ADDR); xgene_ahci_hardreset() 431 writel(portclbhi_saved, port_mmio + PORT_LST_ADDR_HI); xgene_ahci_hardreset() 432 writel(portrxfis_saved, port_mmio + PORT_FIS_ADDR); xgene_ahci_hardreset() 433 writel(portrxfishi_saved, port_mmio + PORT_FIS_ADDR_HI); xgene_ahci_hardreset() 470 void *port_mmio = ahci_port_base(ap); xgene_ahci_pmp_softreset() local 477 port_fbs = readl(port_mmio + PORT_FBS); xgene_ahci_pmp_softreset() 480 writel(port_fbs, port_mmio + PORT_FBS); xgene_ahci_pmp_softreset() 515 void *port_mmio = ahci_port_base(ap); xgene_ahci_softreset() local 521 port_fbs_save = readl(port_mmio + PORT_FBS); xgene_ahci_softreset() 527 port_fbs = readl(port_mmio + PORT_FBS); xgene_ahci_softreset() 530 writel(port_fbs, port_mmio + PORT_FBS); xgene_ahci_softreset() 543 writel(port_fbs_save, port_mmio + PORT_FBS); xgene_ahci_softreset()
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H A D | ahci_qoriq.c | 69 void __iomem *port_mmio = ahci_port_base(link->ap); ahci_qoriq_hardreset() local 97 px_cmd = readl(port_mmio + PORT_CMD); ahci_qoriq_hardreset() 98 px_is = readl(port_mmio + PORT_IRQ_STAT); ahci_qoriq_hardreset() 111 px_val = readl(port_mmio + PORT_CMD); ahci_qoriq_hardreset() 113 writel(px_cmd, port_mmio + PORT_CMD); ahci_qoriq_hardreset() 115 px_val = readl(port_mmio + PORT_IRQ_STAT); ahci_qoriq_hardreset() 117 writel(px_is, port_mmio + PORT_IRQ_STAT); ahci_qoriq_hardreset()
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H A D | ahci_sunxi.c | 157 void __iomem *port_mmio = ahci_port_base(ap); ahci_sunxi_start_engine() local 164 sunxi_setbits(port_mmio + PORT_CMD, PORT_CMD_START); ahci_sunxi_start_engine()
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H A D | pata_pdc2027x.c | 183 * port_mmio - Get the MMIO address of PDC2027x extended registers 187 static inline void __iomem *port_mmio(struct ata_port *ap, unsigned int offset) port_mmio() function 201 return port_mmio(ap, offset) + adj; dev_mmio() 219 cgcr = ioread32(port_mmio(ap, PDC_GLOBAL_CTL)); pdc2027x_cable_detect() 237 return ioread8(port_mmio(ap, PDC_ATA_CTL)) & 0x02; pdc2027x_port_enabled()
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H A D | acard-ahci.c | 339 void __iomem *port_mmio = ahci_port_base(ap); acard_ahci_port_start() local 340 u32 cmd = readl(port_mmio + PORT_CMD); acard_ahci_port_start()
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H A D | ahci.c | 637 void __iomem *port_mmio; ahci_pci_init_controller() local 646 port_mmio = __ahci_port_base(host, mv); ahci_pci_init_controller() 648 writel(0, port_mmio + PORT_IRQ_MASK); ahci_pci_init_controller() 651 tmp = readl(port_mmio + PORT_IRQ_STAT); ahci_pci_init_controller() 654 writel(tmp, port_mmio + PORT_IRQ_STAT); ahci_pci_init_controller()
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