Searched refs:pll_write (Results 1 – 8 of 8) sorted by relevance
/linux-4.4.14/drivers/gpu/drm/msm/dsi/pll/ |
D | dsi_pll_28nm.c | 152 pll_write(base + REG_DSI_28nm_PHY_PLL_POSTDIV2_CFG, 3); in dsi_pll_28nm_clk_set_rate() 163 pll_write(base + REG_DSI_28nm_PHY_PLL_LPFR_CFG, lpfr_lut[i].resistance); in dsi_pll_28nm_clk_set_rate() 166 pll_write(base + REG_DSI_28nm_PHY_PLL_LPFC1_CFG, 0x70); in dsi_pll_28nm_clk_set_rate() 167 pll_write(base + REG_DSI_28nm_PHY_PLL_LPFC2_CFG, 0x15); in dsi_pll_28nm_clk_set_rate() 219 pll_write(base + REG_DSI_28nm_PHY_PLL_CHGPUMP_CFG, 0x02); in dsi_pll_28nm_clk_set_rate() 220 pll_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG3, 0x2b); in dsi_pll_28nm_clk_set_rate() 221 pll_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG4, 0x06); in dsi_pll_28nm_clk_set_rate() 222 pll_write(base + REG_DSI_28nm_PHY_PLL_LKDET_CFG2, 0x0d); in dsi_pll_28nm_clk_set_rate() 224 pll_write(base + REG_DSI_28nm_PHY_PLL_SDM_CFG1, sdm_cfg1); in dsi_pll_28nm_clk_set_rate() 225 pll_write(base + REG_DSI_28nm_PHY_PLL_SDM_CFG2, in dsi_pll_28nm_clk_set_rate() [all …]
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D | dsi_pll.h | 48 static inline void pll_write(void __iomem *reg, u32 data) in pll_write() function 60 pll_write(reg, data); in pll_write_udelay() 66 pll_write((reg), data); in pll_write_ndelay()
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/linux-4.4.14/drivers/gpu/drm/amd/amdgpu/ |
D | atom.h | 121 void (* pll_write)(struct card_info *, uint32_t, uint32_t); /* filled by driver */ member
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D | atom.c | 547 gctx->card->pll_write(gctx->card, idx, val); in atom_put_dst()
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D | amdgpu_device.c | 894 atom_card_info->pll_write = cail_pll_write; in amdgpu_atombios_init()
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/linux-4.4.14/drivers/gpu/drm/radeon/ |
D | atom.h | 121 void (* pll_write)(struct card_info *, uint32_t, uint32_t); /* filled by driver */ member
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D | atom.c | 550 gctx->card->pll_write(gctx->card, idx, val); in atom_put_dst()
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D | radeon_device.c | 979 atom_card_info->pll_write = cail_pll_write; in radeon_atombios_init()
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