Searched refs:outreg (Results 1 - 12 of 12) sorted by relevance

/linux-4.4.14/drivers/video/fbdev/mb862xx/
H A Dmb862xxfbdrv.c102 outreg(disp, GC_L0PAL0 + (regno * 4), val); mb862xxfb_setcolreg()
219 outreg(disp, GC_DCM1, reg); mb862xxfb_set_par()
226 outreg(disp, GC_DCM1, reg); mb862xxfb_set_par()
234 outreg(disp, GC_L0M, reg); mb862xxfb_set_par()
238 outreg(disp, GC_L0EM, reg | GC_L0EM_L0EC_24); mb862xxfb_set_par()
240 outreg(disp, GC_WY_WX, 0); mb862xxfb_set_par()
242 outreg(disp, GC_WH_WW, reg); mb862xxfb_set_par()
243 outreg(disp, GC_L0OA0, 0); mb862xxfb_set_par()
244 outreg(disp, GC_L0DA0, 0); mb862xxfb_set_par()
245 outreg(disp, GC_L0DY_L0DX, 0); mb862xxfb_set_par()
246 outreg(disp, GC_L0WY_L0WX, 0); mb862xxfb_set_par()
247 outreg(disp, GC_L0WH_L0WW, reg); mb862xxfb_set_par()
252 outreg(disp, GC_CPM_CUTC, reg); mb862xxfb_set_par()
256 outreg(disp, GC_HDB_HDP, reg); mb862xxfb_set_par()
258 outreg(disp, GC_VDP_VSP, reg); mb862xxfb_set_par()
261 outreg(disp, GC_VSW_HSW_HSP, reg); mb862xxfb_set_par()
262 outreg(disp, GC_HTP, pack(h_total(&fbi->var) - 1, 0)); mb862xxfb_set_par()
263 outreg(disp, GC_VTR, pack(v_total(&fbi->var) - 1, 0)); mb862xxfb_set_par()
269 outreg(disp, GC_DCM1, reg); mb862xxfb_set_par()
280 outreg(disp, GC_L0WY_L0WX, reg); mb862xxfb_pan()
283 outreg(disp, GC_L0WH_L0WW, reg); mb862xxfb_pan()
298 outreg(disp, GC_DCM1, reg); mb862xxfb_blank()
303 outreg(disp, GC_DCM1, reg); mb862xxfb_blank()
335 outreg(cap, GC_CAP_CSC, mb862xxfb_ioctl()
343 outreg(cap, GC_CAP_CSC, mb862xxfb_ioctl()
346 outreg(cap, GC_CAP_CMSS, mb862xxfb_ioctl()
348 outreg(cap, GC_CAP_CMDS, mb862xxfb_ioctl()
355 outreg(cap, GC_CAP_CBM, mb862xxfb_ioctl()
359 outreg(cap, GC_CAP_CBM, mb862xxfb_ioctl()
363 outreg(disp, GC_L1EM, l1em); mb862xxfb_ioctl()
368 outreg(disp, GC_L1DA, par->cap_buf); mb862xxfb_ioctl()
369 outreg(cap, GC_CAP_IMG_START, mb862xxfb_ioctl()
371 outreg(cap, GC_CAP_IMG_END, mb862xxfb_ioctl()
373 outreg(disp, GC_L1M, GC_L1M_16 | GC_L1M_YC | GC_L1M_CS | mb862xxfb_ioctl()
375 outreg(disp, GC_L1WY_L1WX, mb862xxfb_ioctl()
377 outreg(disp, GC_L1WH_L1WW, mb862xxfb_ioctl()
379 outreg(disp, GC_DLS, 1); mb862xxfb_ioctl()
380 outreg(cap, GC_CAP_VCM, mb862xxfb_ioctl()
382 outreg(disp, GC_DCM1, inreg(disp, GC_DCM1) | mb862xxfb_ioctl()
385 outreg(cap, GC_CAP_VCM, mb862xxfb_ioctl()
387 outreg(disp, GC_DCM1, mb862xxfb_ioctl()
394 outreg(cap, GC_CAP_VCM, mb862xxfb_ioctl()
397 outreg(cap, GC_CAP_VCM, mb862xxfb_ioctl()
537 outreg(cap, GC_CAP_CBM, GC_CBM_OO | GC_CBM_CBST | mb862xxfb_init_fbinfo()
539 outreg(cap, GC_CAP_CBOA, par->cap_buf); mb862xxfb_init_fbinfo()
540 outreg(cap, GC_CAP_CBLA, par->cap_buf + par->cap_len); mb862xxfb_init_fbinfo()
604 outreg(ctrl, 0x0, reg_ist); mb862xx_intr()
615 outreg(host, GC_IST, ~reg_ist); mb862xx_intr()
659 outreg(host, GC_CCF, ccf); mb862xx_gdc_init()
661 outreg(host, GC_MMR, mmr); mb862xx_gdc_init()
666 outreg(host, GC_IST, 0); mb862xx_gdc_init()
667 outreg(host, GC_IMASK, GC_INT_EN); mb862xx_gdc_init()
773 outreg(host, GC_IMASK, 0); of_platform_mb862xx_probe()
800 outreg(disp, GC_DCM1, reg); of_platform_mb862xx_remove()
803 outreg(host, GC_IMASK, 0); of_platform_mb862xx_remove()
881 outreg(host, GC_CCF, GC_CCF_CGE_166 | GC_CCF_COT_133); coralp_init()
883 outreg(host, GC_MMR, GC_MMR_CORALP_EVB_VAL); coralp_init()
887 outreg(host, GC_IST, 0); coralp_init()
904 outreg(dram_ctrl, GC_DCTL_IOCONT1_IOCONT0, GC_EVB_DCTL_IOCONT1_IOCONT0); init_dram_ctrl()
907 outreg(dram_ctrl, GC_DCTL_MODE_ADD, GC_EVB_DCTL_MODE_ADD); init_dram_ctrl()
908 outreg(dram_ctrl, GC_DCTL_SETTIME1_EMODE, GC_EVB_DCTL_SETTIME1_EMODE); init_dram_ctrl()
909 outreg(dram_ctrl, GC_DCTL_REFRESH_SETTIME2, init_dram_ctrl()
911 outreg(dram_ctrl, GC_DCTL_RSV2_RSV1, GC_EVB_DCTL_RSV2_RSV1); init_dram_ctrl()
912 outreg(dram_ctrl, GC_DCTL_DDRIF2_DDRIF1, GC_EVB_DCTL_DDRIF2_DDRIF1); init_dram_ctrl()
913 outreg(dram_ctrl, GC_DCTL_RSV0_STATES, GC_EVB_DCTL_RSV0_STATES); init_dram_ctrl()
923 outreg(dram_ctrl, GC_DCTL_MODE_ADD, GC_EVB_DCTL_MODE_ADD_AFT_RST); init_dram_ctrl()
924 outreg(dram_ctrl, GC_DCTL_RSV0_STATES, GC_EVB_DCTL_RSV0_STATES_AFT_RST); init_dram_ctrl()
946 outreg(ctrl, GC_CTRL_CLK_ENABLE, reg); carmine_init()
956 outreg(ctrl, GC_CTRL_CLK_ENABLE, reg); carmine_init()
962 outreg(ctrl, GC_CTRL_INT_MASK, 0); carmine_init()
966 outreg(ctrl, GC_CTRL_CLK_ENABLE, 0); carmine_init()
1110 outreg(ctrl, GC_CTRL_INT_MASK, GC_CARMINE_INT_EN); mb862xx_pci_probe()
1112 outreg(host, GC_IMASK, GC_INT_EN); mb862xx_pci_probe()
1145 outreg(disp, GC_DCM1, reg); mb862xx_pci_remove()
1148 outreg(ctrl, GC_CTRL_INT_MASK, 0); mb862xx_pci_remove()
1149 outreg(ctrl, GC_CTRL_CLK_ENABLE, 0); mb862xx_pci_remove()
1151 outreg(host, GC_IMASK, 0); mb862xx_pci_remove()
H A Dmb862xx-i2c.c40 outreg(i2c, GC_I2C_DAR, addr); mb862xx_i2c_do_address()
41 outreg(i2c, GC_I2C_CCR, I2C_CLOCK_AND_ENABLE); mb862xx_i2c_do_address()
42 outreg(i2c, GC_I2C_BCR, par->i2c_rs ? I2C_REPEATED_START : I2C_START); mb862xx_i2c_do_address()
53 outreg(i2c, GC_I2C_DAR, byte); mb862xx_i2c_write_byte()
54 outreg(i2c, GC_I2C_BCR, I2C_START); mb862xx_i2c_write_byte()
64 outreg(i2c, GC_I2C_BCR, I2C_START | (last ? 0 : I2C_ACK)); mb862xx_i2c_read_byte()
75 outreg(i2c, GC_I2C_BCR, I2C_STOP); mb862xx_i2c_stop()
76 outreg(i2c, GC_I2C_CCR, I2C_DISABLE); mb862xx_i2c_stop()
H A Dmb862xxfb_accel.c37 outreg(geo, GDC_GEO_REG_INPUT_FIFO, data[total]); mb862xxfb_write_fifo()
319 outreg(disp, GC_L0EM, 3); mb862xxfb_init_accel()
324 outreg(draw, GDC_REG_DRAW_BASE, 0); mb862xxfb_init_accel()
325 outreg(draw, GDC_REG_MODE_MISC, 0x8000); mb862xxfb_init_accel()
326 outreg(draw, GDC_REG_X_RESOLUTION, xres); mb862xxfb_init_accel()
H A Dmb862xxfb.h114 #define outreg(type, off, val) \ macro
/linux-4.4.14/arch/arm/mach-w90x900/
H A Dgpio.c108 void __iomem *outreg = nuc900_gpio->regbase + GPIO_OUT; nuc900_dir_output() local
119 regval = __raw_readl(outreg); nuc900_dir_output()
126 __raw_writel(regval, outreg); nuc900_dir_output()
/linux-4.4.14/drivers/media/dvb-frontends/
H A Ddib7000p.c171 u16 outreg, fifo_threshold, smo_mode; dib7000p_set_output_mode() local
173 outreg = 0; dib7000p_set_output_mode()
181 outreg = (1 << 10); /* 0x0400 */ dib7000p_set_output_mode()
184 outreg = (1 << 10) | (1 << 6); /* 0x0440 */ dib7000p_set_output_mode()
187 outreg = (1 << 10) | (2 << 6) | (0 << 1); /* 0x0480 */ dib7000p_set_output_mode()
191 outreg = (1 << 10) | (4 << 6); /* 0x0500 */ dib7000p_set_output_mode()
193 outreg = (1 << 11); dib7000p_set_output_mode()
198 outreg = (1 << 10) | (5 << 6); dib7000p_set_output_mode()
201 outreg = (1 << 10) | (3 << 6); dib7000p_set_output_mode()
204 outreg = 0; dib7000p_set_output_mode()
217 ret |= dib7000p_write_word(state, 1286, outreg); /* P_Div_active */ dib7000p_set_output_mode()
2598 u16 outreg, smo_mode, fifo_threshold; dib7090_set_output_mode() local
2606 outreg = dib7000p_read_word(state, 1286) & ~((1 << 10) | (0x7 << 6) | (1 << 1)); dib7090_set_output_mode()
2610 outreg = 0; dib7090_set_output_mode()
2621 outreg |= (2<<6) | (0 << 1); dib7090_set_output_mode()
2633 outreg |= (0<<6); dib7090_set_output_mode()
2640 outreg |= (1<<6); dib7090_set_output_mode()
2646 outreg |= (5<<6); dib7090_set_output_mode()
2664 outreg |= (1 << 10); dib7090_set_output_mode()
2671 ret |= dib7000p_write_word(state, 1286, outreg); dib7090_set_output_mode()
H A Ddib7000m.c150 u16 outreg, fifo_threshold, smo_mode, dib7000m_set_output_mode() local
153 outreg = 0; dib7000m_set_output_mode()
161 outreg = (1 << 10); /* 0x0400 */ dib7000m_set_output_mode()
164 outreg = (1 << 10) | (1 << 6); /* 0x0440 */ dib7000m_set_output_mode()
167 outreg = (1 << 10) | (2 << 6) | (0 << 1); /* 0x0482 */ dib7000m_set_output_mode()
171 outreg = (1 << 10) | (4 << 6); /* 0x0500 */ dib7000m_set_output_mode()
178 outreg = (1 << 10) | (5 << 6); dib7000m_set_output_mode()
181 outreg = 0; dib7000m_set_output_mode()
193 ret |= dib7000m_write_word(state, 1795, outreg); dib7000m_set_output_mode()
H A Ddib3000mc.c157 u16 outreg = 0; dib3000mc_set_output_mode() local
205 outreg = dib3000mc_read_word(state, 244) & 0x07FF; dib3000mc_set_output_mode()
206 outreg |= (outmode << 11); dib3000mc_set_output_mode()
207 ret |= dib3000mc_write_word(state, 244, outreg); dib3000mc_set_output_mode()
H A Ddib9000.c1535 u16 outreg, smo_mode; dib9000_fw_set_output_mode() local
1541 outreg = (1 << 10); /* 0x0400 */ dib9000_fw_set_output_mode()
1544 outreg = (1 << 10) | (1 << 6); /* 0x0440 */ dib9000_fw_set_output_mode()
1547 outreg = (1 << 10) | (2 << 6) | (0 << 1); /* 0x0482 */ dib9000_fw_set_output_mode()
1550 outreg = (1 << 10) | (4 << 6); /* 0x0500 */ dib9000_fw_set_output_mode()
1553 outreg = (1 << 10) | (5 << 6); dib9000_fw_set_output_mode()
1556 outreg = 0; dib9000_fw_set_output_mode()
1563 dib9000_write_word(state, 1795, outreg); dib9000_fw_set_output_mode()
1577 outreg = to_fw_output_mode(mode); dib9000_fw_set_output_mode()
1578 return dib9000_mbx_send(state, OUT_MSG_SET_OUTPUT_MODE, &outreg, 1); dib9000_fw_set_output_mode()
H A Ddib8000.c404 u16 outreg, fifo_threshold, smo_mode, sram = 0x0205; /* by default SDRAM deintlv is enabled */ dib8000_set_output_mode() local
407 outreg = 0; dib8000_set_output_mode()
416 outreg = (1 << 10); /* 0x0400 */ dib8000_set_output_mode()
419 outreg = (1 << 10) | (1 << 6); /* 0x0440 */ dib8000_set_output_mode()
422 outreg = (1 << 10) | (2 << 6) | (0 << 1); /* 0x0482 */ dib8000_set_output_mode()
426 outreg = (1 << 10) | (4 << 6); /* 0x0500 */ dib8000_set_output_mode()
434 outreg = (1 << 10) | (5 << 6); dib8000_set_output_mode()
437 outreg = 0; dib8000_set_output_mode()
441 outreg = (1 << 10) | (3 << 6); dib8000_set_output_mode()
456 dib8000_write_word(state, 1286, outreg); dib8000_set_output_mode()
1560 u16 outreg, smo_mode, fifo_threshold; dib8096p_set_output_mode() local
1569 outreg = dib8000_read_word(state, 1286) & dib8096p_set_output_mode()
1574 outreg = 0; dib8096p_set_output_mode()
1586 outreg |= (2 << 6) | (0 << 1); dib8096p_set_output_mode()
1599 outreg |= (0 << 6); dib8096p_set_output_mode()
1606 outreg |= (1 << 6); dib8096p_set_output_mode()
1614 outreg |= (5 << 6); dib8096p_set_output_mode()
1633 outreg |= (1<<10); dib8096p_set_output_mode()
1643 ret |= dib8000_write_word(state, 1286, outreg); dib8096p_set_output_mode()
/linux-4.4.14/drivers/watchdog/
H A Deurotechwdt.c445 goto outreg; eurwdt_init()
466 outreg: eurwdt_init()
H A Dwdt.c617 goto outreg; wdt_init()
656 outreg: wdt_init()

Completed in 286 milliseconds