| H A D | xgmac.c | 100 unsigned int oft = mac->offset; t3_mac_reset() local
102 t3_write_reg(adap, A_XGM_RESET_CTRL + oft, F_MAC_RESET_); t3_mac_reset()
103 t3_read_reg(adap, A_XGM_RESET_CTRL + oft); /* flush */ t3_mac_reset()
105 t3_write_regs(adap, mac_reset_avp, ARRAY_SIZE(mac_reset_avp), oft); t3_mac_reset()
106 t3_set_reg_field(adap, A_XGM_RXFIFO_CFG + oft, t3_mac_reset()
109 t3_set_reg_field(adap, A_XGM_TXFIFO_CFG + oft, 0, F_UNDERUNFIX); t3_mac_reset()
113 t3_set_reg_field(adap, A_XGM_SERDES_CTRL + oft, 0, t3_mac_reset()
115 if (t3_wait_op_done(adap, A_XGM_SERDES_STATUS1 + oft, t3_mac_reset()
122 t3_set_reg_field(adap, A_XGM_SERDES_CTRL + oft, 0, t3_mac_reset()
128 t3_set_reg_field(adap, A_XGM_RX_MAX_PKT_SIZE + oft, t3_mac_reset()
139 t3_write_reg(adap, A_XGM_RESET_CTRL + oft, val); t3_mac_reset()
140 t3_read_reg(adap, A_XGM_RESET_CTRL + oft); /* flush */ t3_mac_reset()
153 unsigned int oft = mac->offset, store; t3b2_mac_reset() local
165 t3_set_reg_field(adap, A_XGM_TX_CFG + oft, F_TXPAUSEEN, 0); t3b2_mac_reset()
167 t3_write_reg(adap, A_XGM_RESET_CTRL + oft, F_MAC_RESET_); t3b2_mac_reset()
168 t3_read_reg(adap, A_XGM_RESET_CTRL + oft); /* flush */ t3b2_mac_reset()
182 if (t3_wait_op_done(adap, A_XGM_RX_MAX_PKT_SIZE_ERR_CNT + oft, t3b2_mac_reset()
189 t3_write_reg(adap, A_XGM_RESET_CTRL + oft, 0); t3b2_mac_reset()
190 t3_read_reg(adap, A_XGM_RESET_CTRL + oft); /* flush */ t3b2_mac_reset()
199 t3_write_reg(adap, A_XGM_RESET_CTRL + oft, val); t3b2_mac_reset()
200 t3_read_reg(adap, A_XGM_RESET_CTRL + oft); /* flush */ t3b2_mac_reset()
205 t3_write_reg(adap, A_XGM_RX_CFG + oft, t3b2_mac_reset()
233 unsigned int oft = mac->offset + idx * 8; set_addr_filter() local
238 t3_write_reg(mac->adapter, A_XGM_RX_EXACT_MATCH_LOW_1 + oft, addr_lo); set_addr_filter()
239 t3_write_reg(mac->adapter, A_XGM_RX_EXACT_MATCH_HIGH_1 + oft, addr_hi); set_addr_filter()
304 unsigned int oft = mac->offset; t3_mac_set_rx_mode() local
306 val = t3_read_reg(adap, A_XGM_RX_CFG + oft) & ~F_COPYALLFRAMES; t3_mac_set_rx_mode()
309 t3_write_reg(adap, A_XGM_RX_CFG + oft, val); t3_mac_set_rx_mode()
332 t3_write_reg(adap, A_XGM_RX_HASH_LOW + oft, hash_lo);
333 t3_write_reg(adap, A_XGM_RX_HASH_HIGH + oft, hash_hi);
432 unsigned int oft = mac->offset; t3_mac_set_speed_duplex_fc() local
448 t3_set_reg_field(adap, A_XGM_PORT_CFG + oft, t3_mac_set_speed_duplex_fc()
452 val = t3_read_reg(adap, A_XGM_RXFIFO_CFG + oft); t3_mac_set_speed_duplex_fc()
457 A_XGM_RX_MAX_PKT_SIZE + oft)); t3_mac_set_speed_duplex_fc()
460 t3_write_reg(adap, A_XGM_RXFIFO_CFG + oft, val); t3_mac_set_speed_duplex_fc()
462 t3_set_reg_field(adap, A_XGM_TX_CFG + oft, F_TXPAUSEEN, t3_mac_set_speed_duplex_fc()
471 unsigned int oft = mac->offset; t3_mac_enable() local
483 t3_write_reg(adap, A_XGM_TX_CTRL + oft, F_TXEN); t3_mac_enable()
491 oft))); t3_mac_enable()
496 oft))); t3_mac_enable()
502 t3_write_reg(adap, A_XGM_RX_CTRL + oft, F_RXEN); t3_mac_enable()
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