Searched refs:msel (Results 1 - 4 of 4) sorted by relevance

/linux-4.4.14/drivers/clk/nxp/
H A Dclk-lpc18xx-cgu.c308 static u32 lpc18xx_pll0_msel2mdec(u32 msel) lpc18xx_pll0_msel2mdec() argument
312 switch (msel) { lpc18xx_pll0_msel2mdec()
317 for (i = msel; i <= LPC18XX_PLL0_MSEL_MAX; i++) lpc18xx_pll0_msel2mdec()
324 static u32 lpc18xx_pll0_msel2seli(u32 msel) lpc18xx_pll0_msel2seli() argument
328 if (msel > 16384) return 1; lpc18xx_pll0_msel2seli()
329 if (msel > 8192) return 2; lpc18xx_pll0_msel2seli()
330 if (msel > 2048) return 4; lpc18xx_pll0_msel2seli()
331 if (msel >= 501) return 8; lpc18xx_pll0_msel2seli()
332 if (msel >= 60) { lpc18xx_pll0_msel2seli()
333 tmp = 1024 / (msel + 9); lpc18xx_pll0_msel2seli()
334 return ((1024 == (tmp * (msel + 9))) == 0) ? tmp * 4 : (tmp + 1) * 4; lpc18xx_pll0_msel2seli()
337 return (msel & 0x3c) + 4; lpc18xx_pll0_msel2seli()
341 static u32 lpc18xx_pll0_msel2selp(u32 msel) lpc18xx_pll0_msel2selp() argument
343 if (msel < 60) lpc18xx_pll0_msel2selp()
344 return (msel >> 1) + 1; lpc18xx_pll0_msel2selp()
353 u32 ctrl, mdiv, msel, npdiv; lpc18xx_pll0_recalc_rate() local
367 msel = lpc18xx_pll0_mdec2msel(mdiv & LPC18XX_PLL0_MDIV_MDEC_MASK); lpc18xx_pll0_recalc_rate()
368 if (msel) lpc18xx_pll0_recalc_rate()
369 return 2 * msel * parent_rate; lpc18xx_pll0_recalc_rate()
457 u16 msel, nsel, psel; lpc18xx_pll1_recalc_rate() local
467 msel = ((ctrl >> 16) & 0xff) + 1; lpc18xx_pll1_recalc_rate()
471 return msel * (parent_rate / nsel); lpc18xx_pll1_recalc_rate()
476 return (msel / (2 * psel)) * (parent_rate / nsel); lpc18xx_pll1_recalc_rate()
/linux-4.4.14/arch/blackfin/mach-bf609/
H A Dclock.c141 u32 msel; pll_get_rate() local
146 msel = (ctl & CGU0_CTL_MSEL_MASK) >> CGU0_CTL_MSEL_SHIFT; pll_get_rate()
149 return clk->parent->rate / (df + 1) * msel * 2; pll_get_rate()
161 u32 msel; pll_set_rate() local
169 msel = rate / clk->parent->rate / 2; pll_set_rate()
170 clk_reg_write_mask(CGU0_CTL, msel << CGU0_CTL_MSEL_SHIFT, pll_set_rate()
187 u32 msel; sys_clk_get_rate() local
192 msel = (ctl & CGU0_CTL_MSEL_MASK) >> CGU0_CTL_MSEL_SHIFT; sys_clk_get_rate()
197 drate *= msel; sys_clk_get_rate()
217 u32 msel; sys_clk_round_rate() local
221 msel = (ctl & CGU0_CTL_MSEL_MASK) >> CGU0_CTL_MSEL_SHIFT; sys_clk_round_rate()
223 max_rate = clk->parent->rate / (df + 1) * msel; sys_clk_round_rate()
/linux-4.4.14/drivers/fpga/
H A Dsocfpga.c333 u32 msel; socfpga_fpga_cfg_mode_get() local
335 msel = socfpga_fpga_readl(priv, SOCFPGA_FPGMGR_STAT_OFST); socfpga_fpga_cfg_mode_get()
336 msel &= SOCFPGA_FPGMGR_STAT_MSEL_MASK; socfpga_fpga_cfg_mode_get()
337 msel >>= SOCFPGA_FPGMGR_STAT_MSEL_SHIFT; socfpga_fpga_cfg_mode_get()
340 if ((msel >= ARRAY_SIZE(cfgmgr_modes)) || !cfgmgr_modes[msel].valid) socfpga_fpga_cfg_mode_get()
343 return msel; socfpga_fpga_cfg_mode_get()
/linux-4.4.14/arch/blackfin/kernel/
H A Dsetup.c1149 u_long msel, pll_ctl; get_vco() local
1158 msel = (pll_ctl >> 9) & 0x3F; get_vco()
1159 if (0 == msel) get_vco()
1160 msel = 64; get_vco()
1164 cached_vco *= msel; get_vco()

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