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Searched refs:mmSDMA0_F32_CNTL (Results 1 – 9 of 9) sorted by relevance

/linux-4.4.14/drivers/gpu/drm/amd/amdgpu/
Dvi.c735 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET); in vi_gpu_soft_reset()
737 WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp); in vi_gpu_soft_reset()
741 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET); in vi_gpu_soft_reset()
743 WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp); in vi_gpu_soft_reset()
885 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET); in vi_gpu_pci_config_reset()
887 WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp); in vi_gpu_pci_config_reset()
890 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET); in vi_gpu_pci_config_reset()
892 WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp); in vi_gpu_pci_config_reset()
Dcik_sdma.c380 me_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]); in cik_sdma_enable()
385 WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], me_cntl); in cik_sdma_enable()
1077 i, RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i])); in cik_sdma_print_status()
1122 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET); in cik_sdma_soft_reset()
1124 WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp); in cik_sdma_soft_reset()
1129 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET); in cik_sdma_soft_reset()
1131 WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp); in cik_sdma_soft_reset()
Dsdma_v2_4.c423 f32_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]); in sdma_v2_4_enable()
428 WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], f32_cntl); in sdma_v2_4_enable()
1093 i, RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i])); in sdma_v2_4_print_status()
1136 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET); in sdma_v2_4_soft_reset()
1138 WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp); in sdma_v2_4_soft_reset()
1143 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET); in sdma_v2_4_soft_reset()
1145 WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp); in sdma_v2_4_soft_reset()
Dcik.c1188 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET); in cik_gpu_soft_reset()
1190 WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp); in cik_gpu_soft_reset()
1194 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET); in cik_gpu_soft_reset()
1196 WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp); in cik_gpu_soft_reset()
1394 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET); in cik_gpu_pci_config_reset()
1396 WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp); in cik_gpu_pci_config_reset()
1398 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET); in cik_gpu_pci_config_reset()
1400 WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp); in cik_gpu_pci_config_reset()
Dsdma_v3_0.c559 f32_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]); in sdma_v3_0_enable()
564 WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], f32_cntl); in sdma_v3_0_enable()
1253 i, RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i])); in sdma_v3_0_print_status()
1298 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET); in sdma_v3_0_soft_reset()
1300 WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp); in sdma_v3_0_soft_reset()
1305 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET); in sdma_v3_0_soft_reset()
1307 WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp); in sdma_v3_0_soft_reset()
/linux-4.4.14/drivers/gpu/drm/amd/include/asic_reg/oss/
Doss_2_4_d.h174 #define mmSDMA0_F32_CNTL 0x3412 macro
Doss_3_0_1_d.h172 #define mmSDMA0_F32_CNTL 0x3412 macro
Doss_3_0_d.h309 #define mmSDMA0_F32_CNTL 0x3412 macro
Doss_2_0_d.h237 #define mmSDMA0_F32_CNTL 0x3412 macro