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Searched refs:mmCRTC_CONTROL (Results 1 – 6 of 6) sorted by relevance

/linux-4.4.14/drivers/gpu/drm/amd/amdgpu/
Ddce_v8_0.c178 if (!(RREG32(mmCRTC_CONTROL + crtc_offsets[crtc]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK)) in dce_v8_0_vblank_wait()
485 if (RREG32(mmCRTC_CONTROL + crtc_offsets[i]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK) { in dce_v8_0_is_display_hung()
523 crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]), in dce_v8_0_stop_mc_access()
559 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]); in dce_v8_0_stop_mc_access()
561 WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp); in dce_v8_0_stop_mc_access()
Ddce_v11_0.c219 if (!(RREG32(mmCRTC_CONTROL + crtc_offsets[crtc]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK)) in dce_v11_0_vblank_wait()
524 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]); in dce_v11_0_is_display_hung()
563 crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]), in dce_v11_0_stop_mc_access()
599 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]); in dce_v11_0_stop_mc_access()
601 WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp); in dce_v11_0_stop_mc_access()
Ddce_v10_0.c229 if (!(RREG32(mmCRTC_CONTROL + crtc_offsets[crtc]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK)) in dce_v10_0_vblank_wait()
536 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]); in dce_v10_0_is_display_hung()
575 crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]), in dce_v10_0_stop_mc_access()
611 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]); in dce_v10_0_stop_mc_access()
613 WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp); in dce_v10_0_stop_mc_access()
/linux-4.4.14/drivers/gpu/drm/amd/include/asic_reg/dce/
Ddce_8_0_d.h333 #define mmCRTC_CONTROL 0x1b9c macro
Ddce_11_0_d.h315 #define mmCRTC_CONTROL 0x1b9c macro
Ddce_10_0_d.h388 #define mmCRTC_CONTROL 0x1b9c macro