Searched refs:mclk_table (Results 1 - 4 of 4) sorted by relevance

/linux-4.4.14/drivers/gpu/drm/radeon/
H A Dci_dpm.c2526 for (j = 0; j < pi->dpm_table.mclk_table.count; j++) { ci_do_program_memory_timing_parameters()
2529 pi->dpm_table.mclk_table.dpm_levels[j].value, ci_do_program_memory_timing_parameters()
3306 for (i = 0; i < dpm_table->mclk_table.count; i++) { ci_populate_all_memory_levels()
3307 if (dpm_table->mclk_table.dpm_levels[i].value == 0) ci_populate_all_memory_levels()
3310 dpm_table->mclk_table.dpm_levels[i].value, ci_populate_all_memory_levels()
3318 if ((dpm_table->mclk_table.count >= 2) && ci_populate_all_memory_levels()
3328 pi->smc_state_table.MemoryDpmLevelCount = (u8)dpm_table->mclk_table.count; ci_populate_all_memory_levels()
3330 ci_get_dpm_level_enable_mask_value(&dpm_table->mclk_table); ci_populate_all_memory_levels()
3332 pi->smc_state_table.MemoryLevel[dpm_table->mclk_table.count - 1].DisplayWatermark = ci_populate_all_memory_levels()
3437 &pi->dpm_table.mclk_table, ci_setup_default_dpm_tables()
3462 pi->dpm_table.mclk_table.count = 0; ci_setup_default_dpm_tables()
3465 (pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count-1].value != ci_setup_default_dpm_tables()
3467 pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count].value = ci_setup_default_dpm_tables()
3469 pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count].enabled = ci_setup_default_dpm_tables()
3471 pi->dpm_table.mclk_table.count++; ci_setup_default_dpm_tables()
3603 ret = ci_find_boot_level(&pi->dpm_table.mclk_table, ci_init_smc_table()
3740 &pi->dpm_table.mclk_table, ci_trim_dpm_states()
3832 struct ci_single_dpm_table *mclk_table = &pi->dpm_table.mclk_table; ci_find_dpm_states_clocks_in_dpm_table() local
3851 for (i = 0; i < mclk_table->count; i++) { ci_find_dpm_states_clocks_in_dpm_table()
3852 if (mclk == mclk_table->dpm_levels[i].value) ci_find_dpm_states_clocks_in_dpm_table()
3856 if (i >= mclk_table->count) ci_find_dpm_states_clocks_in_dpm_table()
3881 dpm_table->mclk_table.dpm_levels[dpm_table->mclk_table.count-1].value = mclk; ci_populate_and_upload_sclk_mclk_dpm_levels()
4148 ci_get_dpm_level_enable_mask_value(&pi->dpm_table.mclk_table); ci_generate_dpm_level_enable_mask()
4711 for (i = 0; i < pi->dpm_table.mclk_table.count; i++) ci_convert_mc_reg_table_to_smc()
4713 pi->dpm_table.mclk_table.dpm_levels[i].value, ci_convert_mc_reg_table_to_smc()
4752 pi->dpm_table.mclk_table.count, ci_update_and_upload_mc_reg_table()
H A Dci_dpm.h69 struct ci_single_dpm_table mclk_table; member in struct:ci_dpm_table
/linux-4.4.14/drivers/gpu/drm/amd/amdgpu/
H A Dci_dpm.c2656 for (j = 0; j < pi->dpm_table.mclk_table.count; j++) { ci_do_program_memory_timing_parameters()
2659 pi->dpm_table.mclk_table.dpm_levels[j].value, ci_do_program_memory_timing_parameters()
3444 for (i = 0; i < dpm_table->mclk_table.count; i++) { ci_populate_all_memory_levels()
3445 if (dpm_table->mclk_table.dpm_levels[i].value == 0) ci_populate_all_memory_levels()
3448 dpm_table->mclk_table.dpm_levels[i].value, ci_populate_all_memory_levels()
3454 if ((dpm_table->mclk_table.count >= 2) && ci_populate_all_memory_levels()
3464 pi->smc_state_table.MemoryDpmLevelCount = (u8)dpm_table->mclk_table.count; ci_populate_all_memory_levels()
3466 ci_get_dpm_level_enable_mask_value(&dpm_table->mclk_table); ci_populate_all_memory_levels()
3468 pi->smc_state_table.MemoryLevel[dpm_table->mclk_table.count - 1].DisplayWatermark = ci_populate_all_memory_levels()
3573 &pi->dpm_table.mclk_table, ci_setup_default_dpm_tables()
3598 pi->dpm_table.mclk_table.count = 0; ci_setup_default_dpm_tables()
3601 (pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count-1].value != ci_setup_default_dpm_tables()
3603 pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count].value = ci_setup_default_dpm_tables()
3605 pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count].enabled = ci_setup_default_dpm_tables()
3607 pi->dpm_table.mclk_table.count++; ci_setup_default_dpm_tables()
3739 ret = ci_find_boot_level(&pi->dpm_table.mclk_table, ci_init_smc_table()
3876 &pi->dpm_table.mclk_table, ci_trim_dpm_states()
3970 struct ci_single_dpm_table *mclk_table = &pi->dpm_table.mclk_table; ci_find_dpm_states_clocks_in_dpm_table() local
3989 for (i = 0; i < mclk_table->count; i++) { ci_find_dpm_states_clocks_in_dpm_table()
3990 if (mclk == mclk_table->dpm_levels[i].value) ci_find_dpm_states_clocks_in_dpm_table()
3994 if (i >= mclk_table->count) ci_find_dpm_states_clocks_in_dpm_table()
4019 dpm_table->mclk_table.dpm_levels[dpm_table->mclk_table.count-1].value = mclk; ci_populate_and_upload_sclk_mclk_dpm_levels()
4292 ci_get_dpm_level_enable_mask_value(&pi->dpm_table.mclk_table); ci_generate_dpm_level_enable_mask()
4880 for (i = 0; i < pi->dpm_table.mclk_table.count; i++) ci_convert_mc_reg_table_to_smc()
4882 pi->dpm_table.mclk_table.dpm_levels[i].value, ci_convert_mc_reg_table_to_smc()
4921 pi->dpm_table.mclk_table.count, ci_update_and_upload_mc_reg_table()
H A Dci_dpm.h70 struct ci_single_dpm_table mclk_table; member in struct:ci_dpm_table

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