| H A D | lgdt3305.c | 115 static int lgdt3305_write_reg(struct lgdt3305_state *state, u16 reg, u8 val) lgdt3305_write_reg() function
189 ret = lgdt3305_write_reg(state, reg, val); lgdt3305_set_reg_bit()
207 ret = lgdt3305_write_reg(state, regs[i].reg, regs[i].val); lgdt3305_write_regs()
262 ret = lgdt3305_write_reg(state, LGDT3305_TP_CTRL_1, val); lgdt3305_mpeg_mode_polarity()
298 ret = lgdt3305_write_reg(state, LGDT3305_GEN_CTRL_1, opermode); lgdt3305_set_modulation()
347 lgdt3305_write_reg(state, LGDT3305_DGTL_AGC_REF_1, agc_ref >> 8); lgdt3305_passband_digital_agc()
348 lgdt3305_write_reg(state, LGDT3305_DGTL_AGC_REF_2, agc_ref & 0xff); lgdt3305_passband_digital_agc()
383 lgdt3305_write_reg(state, LGDT3305_AGC_DELAY_PT_1, lgdt3305_rfagc_loop()
385 lgdt3305_write_reg(state, LGDT3305_AGC_DELAY_PT_2, lgdt3305_rfagc_loop()
388 lgdt3305_write_reg(state, LGDT3305_RFAGC_LOOP_FLTR_BW_1, lgdt3305_rfagc_loop()
390 lgdt3305_write_reg(state, LGDT3305_RFAGC_LOOP_FLTR_BW_2, lgdt3305_rfagc_loop()
396 lgdt3305_write_reg(state, LGDT3305_IFBW_1, ifbw >> 8); lgdt3305_rfagc_loop()
397 lgdt3305_write_reg(state, LGDT3305_IFBW_2, ifbw & 0xff); lgdt3305_rfagc_loop()
427 lgdt3305_write_reg(state, 0x0314, 0xe1 | lockdten << 1); lgdt3305_agc_setup()
431 lgdt3305_write_reg(state, LGDT3305_AGC_CTRL_4, 0xe1 | lockdten << 1); lgdt3305_agc_setup()
468 lgdt3305_write_reg(state, LGDT3305_AGC_POWER_REF_1, lgdt3305_set_agc_power_ref()
470 lgdt3305_write_reg(state, LGDT3305_AGC_POWER_REF_2, lgdt3305_set_agc_power_ref()
488 ret = lgdt3305_write_reg(state, LGDT3305_CR_CTRL_7, lgdt3305_spectral_inversion()
493 ret = lgdt3305_write_reg(state, LGDT3305_FEC_BLOCK_CTRL, lgdt3305_spectral_inversion()
543 lgdt3305_write_reg(state, LGDT3305_CR_CTR_FREQ_1, nco1); lgdt3305_set_if()
544 lgdt3305_write_reg(state, LGDT3305_CR_CTR_FREQ_2, nco2); lgdt3305_set_if()
545 lgdt3305_write_reg(state, LGDT3305_CR_CTR_FREQ_3, nco3); lgdt3305_set_if()
546 lgdt3305_write_reg(state, LGDT3305_CR_CTR_FREQ_4, nco4); lgdt3305_set_if()
591 lgdt3305_write_reg(state, LGDT3305_GEN_CTRL_3, gen_ctrl_3); lgdt3305_sleep()
592 lgdt3305_write_reg(state, LGDT3305_GEN_CTRL_4, gen_ctrl_4); lgdt3305_sleep()
715 lgdt3305_write_reg(state, 0x030d, 0x00); lgdt3304_set_parameters()
716 lgdt3305_write_reg(state, LGDT3305_CR_CTR_FREQ_1, 0x4f); lgdt3304_set_parameters()
717 lgdt3305_write_reg(state, LGDT3305_CR_CTR_FREQ_2, 0x0c); lgdt3304_set_parameters()
718 lgdt3305_write_reg(state, LGDT3305_CR_CTR_FREQ_3, 0xac); lgdt3304_set_parameters()
719 lgdt3305_write_reg(state, LGDT3305_CR_CTR_FREQ_4, 0xba); lgdt3304_set_parameters()
723 lgdt3305_write_reg(state, 0x030d, 0x14); lgdt3304_set_parameters()
783 ret = lgdt3305_write_reg(state, LGDT3305_GEN_CONTROL, 0x2f); lgdt3305_set_parameters()
1145 ret = lgdt3305_write_reg(state, 0x0808, 0x80); lgdt3305_attach()
1151 ret = lgdt3305_write_reg(state, 0x0808, 0x00); lgdt3305_attach()
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