| H A D | designware_i2s.c | 92 void __iomem *i2s_base; member in struct:dw_i2s_dev
121 i2s_write_reg(dev->i2s_base, TER(i), 0); i2s_disable_channels()
124 i2s_write_reg(dev->i2s_base, RER(i), 0); i2s_disable_channels()
134 i2s_read_reg(dev->i2s_base, TOR(i)); i2s_clear_irqs()
137 i2s_read_reg(dev->i2s_base, ROR(i)); i2s_clear_irqs()
145 i2s_write_reg(dev->i2s_base, IER, 1); i2s_start()
149 irq = i2s_read_reg(dev->i2s_base, IMR(i)); i2s_start()
150 i2s_write_reg(dev->i2s_base, IMR(i), irq & ~0x30); i2s_start()
152 i2s_write_reg(dev->i2s_base, ITER, 1); i2s_start()
155 irq = i2s_read_reg(dev->i2s_base, IMR(i)); i2s_start()
156 i2s_write_reg(dev->i2s_base, IMR(i), irq & ~0x03); i2s_start()
158 i2s_write_reg(dev->i2s_base, IRER, 1); i2s_start()
161 i2s_write_reg(dev->i2s_base, CER, 1); i2s_start()
171 i2s_write_reg(dev->i2s_base, ITER, 0); i2s_stop()
174 irq = i2s_read_reg(dev->i2s_base, IMR(i)); i2s_stop()
175 i2s_write_reg(dev->i2s_base, IMR(i), irq | 0x30); i2s_stop()
178 i2s_write_reg(dev->i2s_base, IRER, 0); i2s_stop()
181 irq = i2s_read_reg(dev->i2s_base, IMR(i)); i2s_stop()
182 i2s_write_reg(dev->i2s_base, IMR(i), irq | 0x03); i2s_stop()
187 i2s_write_reg(dev->i2s_base, CER, 0); i2s_stop()
188 i2s_write_reg(dev->i2s_base, IER, 0); i2s_stop()
265 i2s_write_reg(dev->i2s_base, TCR(ch_reg), dw_i2s_hw_params()
267 i2s_write_reg(dev->i2s_base, TFCR(ch_reg), 0x02); dw_i2s_hw_params()
268 irq = i2s_read_reg(dev->i2s_base, IMR(ch_reg)); dw_i2s_hw_params()
269 i2s_write_reg(dev->i2s_base, IMR(ch_reg), irq & ~0x30); dw_i2s_hw_params()
270 i2s_write_reg(dev->i2s_base, TER(ch_reg), 1); dw_i2s_hw_params()
272 i2s_write_reg(dev->i2s_base, RCR(ch_reg), dw_i2s_hw_params()
274 i2s_write_reg(dev->i2s_base, RFCR(ch_reg), 0x07); dw_i2s_hw_params()
275 irq = i2s_read_reg(dev->i2s_base, IMR(ch_reg)); dw_i2s_hw_params()
276 i2s_write_reg(dev->i2s_base, IMR(ch_reg), irq & ~0x03); dw_i2s_hw_params()
277 i2s_write_reg(dev->i2s_base, RER(ch_reg), 1); dw_i2s_hw_params()
281 i2s_write_reg(dev->i2s_base, CCR, ccr); dw_i2s_hw_params()
319 i2s_write_reg(dev->i2s_base, TXFFR, 1); dw_i2s_prepare()
321 i2s_write_reg(dev->i2s_base, RXFFR, 1); dw_i2s_prepare()
462 u32 comp1 = i2s_read_reg(dev->i2s_base, I2S_COMP_PARAM_1); dw_configure_dai()
463 u32 comp2 = i2s_read_reg(dev->i2s_base, I2S_COMP_PARAM_2); dw_configure_dai()
506 u32 comp1 = i2s_read_reg(dev->i2s_base, I2S_COMP_PARAM_1); dw_configure_dai_by_pd()
536 u32 comp1 = i2s_read_reg(dev->i2s_base, I2S_COMP_PARAM_1); dw_configure_dai_by_dt()
537 u32 comp2 = i2s_read_reg(dev->i2s_base, I2S_COMP_PARAM_2); dw_configure_dai_by_dt()
601 dev->i2s_base = devm_ioremap_resource(&pdev->dev, res); dw_i2s_probe()
602 if (IS_ERR(dev->i2s_base)) dw_i2s_probe()
603 return PTR_ERR(dev->i2s_base); dw_i2s_probe()
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