Searched refs:engines (Results 1 - 139 of 139) sorted by relevance

/linux-4.4.14/drivers/crypto/marvell/
H A Dcesa.c124 spin_lock_bh(&cesa_dev->engines[i].lock); mv_cesa_queue_req()
125 if (!cesa_dev->engines[i].req) mv_cesa_queue_req()
126 mv_cesa_dequeue_req_unlocked(&cesa_dev->engines[i]); mv_cesa_queue_req()
127 spin_unlock_bh(&cesa_dev->engines[i].lock); mv_cesa_queue_req()
320 struct mv_cesa_engine *engine = &cesa->engines[idx]; mv_cesa_get_sram()
362 struct mv_cesa_engine *engine = &cesa->engines[idx]; mv_cesa_put_sram()
378 struct mv_cesa_engine *engines; mv_cesa_probe() local
413 cesa->engines = devm_kzalloc(dev, caps->nengines * sizeof(*engines), mv_cesa_probe()
415 if (!cesa->engines) mv_cesa_probe()
434 struct mv_cesa_engine *engine = &cesa->engines[i]; mv_cesa_probe()
478 mv_cesa_conf_mbus_windows(&cesa->engines[i], dram); mv_cesa_probe()
480 writel(0, cesa->engines[i].regs + CESA_SA_INT_STATUS); mv_cesa_probe()
482 cesa->engines[i].regs + CESA_SA_CFG); mv_cesa_probe()
484 cesa->engines[i].regs + CESA_SA_DESC_P0); mv_cesa_probe()
489 &cesa->engines[i]); mv_cesa_probe()
508 clk_disable_unprepare(cesa->engines[i].zclk); mv_cesa_probe()
509 clk_disable_unprepare(cesa->engines[i].clk); mv_cesa_probe()
524 clk_disable_unprepare(cesa->engines[i].zclk); mv_cesa_remove()
525 clk_disable_unprepare(cesa->engines[i].clk); mv_cesa_remove()
H A Dcesa.h359 * @engines: number of engines
402 * @engines: array of engines
414 struct mv_cesa_engine *engines; member in struct:mv_cesa_dev
/linux-4.4.14/sound/soc/sh/
H A DMakefile1 ## DMA engines
/linux-4.4.14/drivers/media/platform/xilinx/
H A Dxilinx-dma.h35 * @use_count: number of DMA engines using the pipeline
36 * @stream_count: number of DMA engines currently streaming
37 * @num_dmas: number of DMA engines in the pipeline
H A Dxilinx-dma.c136 * The pipeline is shared between all DMA engines connect at its input and
137 * output. While the stream state of DMA engines can be controlled
140 * counter that tracks the number of DMA engines that have requested the stream
145 * DMA engines in the pipeline it will enable all entities that belong to the
H A Dxilinx-vipp.c122 /* Skip DMA engines, they will be processed separately. */ xvip_graph_build_one()
203 dev_dbg(xdev->dev, "creating links for DMA engines\n"); xvip_graph_build_dma()
/linux-4.4.14/arch/mips/cavium-octeon/executive/
H A Dcvmx-helper-npi.c56 /* The packet engines didn't exist before pass 2 */ __cvmx_helper_npi_probe()
60 /* The packet engines didn't exist before pass 2 */ __cvmx_helper_npi_probe()
65 * engines, but nobody ever uses them. Since this is the case, __cvmx_helper_npi_probe()
/linux-4.4.14/drivers/gpu/drm/nouveau/nvkm/engine/fifo/
H A Dchan.h23 u64 engines, int bar, u32 base, u32 user,
H A Dgpfifogk104.c215 u32 engines; gk104_fifo_gpfifo_new() local
227 /* determine which downstream engines are present */ gk104_fifo_gpfifo_new()
228 for (i = 0, engines = 0; i < ARRAY_SIZE(fifo->engine); i++) { gk104_fifo_gpfifo_new()
232 engines |= (1 << i); gk104_fifo_gpfifo_new()
237 args->v0.engine = engines; gk104_fifo_gpfifo_new()
245 args->v0.engine &= engines; gk104_fifo_gpfifo_new()
H A Dchan.c208 u64 mask = chan->engines; nvkm_fifo_chan_child_get()
350 u64 vm, u64 push, u64 engines, int bar, u32 base, u32 user, nvkm_fifo_chan_ctor()
364 chan->engines = engines; nvkm_fifo_chan_ctor()
348 nvkm_fifo_chan_ctor(const struct nvkm_fifo_chan_func *func, struct nvkm_fifo *fifo, u32 size, u32 align, bool zero, u64 vm, u64 push, u64 engines, int bar, u32 base, u32 user, const struct nvkm_oclass *oclass, struct nvkm_fifo_chan *chan) nvkm_fifo_chan_ctor() argument
H A Dchannv50.c62 * PFIFO will hang forever if the connected engines don't report nv50_fifo_chan_engine_fini()
66 * connected engines are in a state where they can answer. nv50_fifo_chan_engine_fini()
69 * there's also a "ignore these engines" bitmask reg we can use nv50_fifo_chan_engine_fini()
H A Dgf100.c580 /* assign engines to PBDMAs */ gf100_fifo_init()
/linux-4.4.14/drivers/dma/ppc4xx/
H A Ddma.h2 * 440SPe's DMA engines support header file
20 /* Number of DMA engines available on the contoller */
103 * DMAx engines Command Descriptor Block Type
H A Dxor.h2 * 440SPe's XOR engines support header file
18 /* Number of XOR engines available on the contoller */
H A Dadma.c24 * This driver supports the asynchrounous DMA copy and RAID engines available
1359 * else let it be processed on one of the DMA0/1 engines. ppc440spe_adma_estimate()
3667 * ppc440spe_chan_start_null_xor - initiate the first XOR operation (DMA engines
3924 /* only DMA engines have a separate error IRQ ppc440spe_adma_setup_irqs()
3928 /* both DMA engines share common error IRQ */ ppc440spe_adma_setup_irqs()
4052 /* DMA0,1 engines use FIFO to maintain CDBs, so we ppc440spe_adma_probe()
4309 * "devices" shows available engines.
4420 * Common initialisation for RAID engines; allocate memory for
4421 * DMAx FIFOs, perform configuration common for all DMA engines.
/linux-4.4.14/drivers/gpu/drm/nouveau/include/nvkm/engine/
H A Dfifo.h17 u64 engines; member in struct:nvkm_fifo_chan
/linux-4.4.14/drivers/gpu/drm/radeon/
H A Dcik_sdma.c41 * DMA engines. These engines are used for compute
42 * and gfx. There are two DMA engines (SDMA0, SDMA1)
244 * cik_sdma_gfx_stop - stop the gfx async dma engines
285 * cik_sdma_rlc_stop - stop the compute async dma engines
302 * Halt or unhalt the async dma engines (CIK).
324 * cik_sdma_enable - stop the async dma engines
329 * Halt or unhalt the async dma engines (CIK).
358 * cik_sdma_gfx_resume - setup and start the async dma engines
441 * cik_sdma_rlc_resume - setup and start the async dma engines
521 * cik_sdma_resume - setup and start the async dma engines
525 * Set up the DMA engines and enable them (CIK).
551 * cik_sdma_fini - tear down the async dma engines
555 * Stop the async dma engines and free the rings (CIK).
H A Dni_dma.c42 * Cayman and newer support two asynchronous DMA engines.
151 * cayman_dma_stop - stop the async dma engines
155 * Stop the async dma engines (cayman-SI).
180 * cayman_dma_resume - setup and start the async dma engines
265 * cayman_dma_fini - tear down the async dma engines
269 * Stop the async dma engines and free the rings (cayman-SI).
H A Dradeon_ib.c112 * On SI, there are two parallel engines fed from the primary ring,
H A Dradeon_ring.c34 * Most engines on the GPU are fed via ring buffers. Ring
H A Dcik.c3449 * @se_num: number of SEs (shader engines) for the asic
3479 * @se_num: number of SEs (shader engines) for the asic
5577 /* XXX other engines? */ cik_gpu_pci_config_reset()
H A Devergreen.c4113 /* XXX other engines? */ evergreen_gpu_pci_config_reset()
H A Dr100.c503 * Check of the GUI (2D/3D engines) are idle (r1xx-r5xx).
H A Dsi.c4055 /* XXX other engines? */ si_gpu_pci_config_reset()
H A Datombios.h3178 // = 3-7 Reserved for future I2C engines
/linux-4.4.14/drivers/gpu/drm/omapdrm/
H A Domap_dmm_tiler.c151 if (dmm->engines[i].async) omap_dmm_irq_handler()
152 release_engine(&dmm->engines[i]); omap_dmm_irq_handler()
154 complete(&dmm->engines[i].compl); omap_dmm_irq_handler()
571 kfree(omap_dmm->engines); omap_dmm_remove()
709 /* alloc engines */ omap_dmm_probe()
710 omap_dmm->engines = kcalloc(omap_dmm->num_engines, omap_dmm_probe()
712 if (!omap_dmm->engines) { omap_dmm_probe()
718 omap_dmm->engines[i].id = i; omap_dmm_probe()
719 omap_dmm->engines[i].dmm = omap_dmm; omap_dmm_probe()
720 omap_dmm->engines[i].refill_va = omap_dmm->refill_va + omap_dmm_probe()
722 omap_dmm->engines[i].refill_pa = omap_dmm->refill_pa + omap_dmm_probe()
724 init_completion(&omap_dmm->engines[i].compl); omap_dmm_probe()
726 list_add(&omap_dmm->engines[i].idle_node, &omap_dmm->idle_head); omap_dmm_probe()
H A Domap_dmm_priv.h171 /* refill engines */
174 struct refill_engine *engines; member in struct:dmm
/linux-4.4.14/drivers/leds/
H A Dleds-lp55xx-common.h146 * @engines : Engine structure for the device attribute R/W interface
157 struct lp55xx_engine engines[LP55XX_ENGINE_MAX]; member in struct:lp55xx_chip
H A Dleds-lp5521.c335 /* Set engines are set to run state when OP_MODE enables engines */ lp5521_post_init_device()
383 enum lp55xx_engine_mode mode = chip->engines[nr - 1].mode; show_engine_mode()
405 struct lp55xx_engine *engine = &chip->engines[nr - 1]; store_engine_mode()
H A Dleds-lp5523.c405 enum lp55xx_engine_mode mode = chip->engines[nr - 1].mode; show_engine_mode()
427 struct lp55xx_engine *engine = &chip->engines[nr - 1]; store_engine_mode()
496 lp5523_mux_to_array(chip->engines[nr - 1].led_mux, mux); show_engine_leds()
506 struct lp55xx_engine *engine = &chip->engines[nr - 1]; lp5523_load_mux()
538 struct lp55xx_engine *engine = &chip->engines[nr - 1]; store_engine_leds()
H A Dleds-lp5562.c375 /* Load engines */ lp5562_run_predef_led_pattern()
389 /* Program engines */ lp5562_run_predef_led_pattern()
397 /* Run engines */ lp5562_run_predef_led_pattern()
H A Dleds-lp55xx-common.c209 chip->engines[idx - 1].mode = LP55XX_ENGINE_LOAD; lp55xx_firmware_loaded()
/linux-4.4.14/drivers/gpu/drm/amd/amdgpu/
H A Dcik_sdma.c72 * DMA engines. These engines are used for compute
73 * and gfx. There are two DMA engines (SDMA0, SDMA1)
322 * cik_sdma_gfx_stop - stop the gfx async dma engines
350 * cik_sdma_rlc_stop - stop the compute async dma engines
362 * cik_sdma_enable - stop the async dma engines
367 * Halt or unhalt the async dma engines (CIK).
390 * cik_sdma_gfx_resume - setup and start the async dma engines
477 * cik_sdma_rlc_resume - setup and start the async dma engines
530 * cik_sdma_start - setup and start the async dma engines
534 * Set up the DMA engines and enable them (CIK).
H A Dsdma_v2_4.c78 * DMA engines. These engines are used for compute
79 * and gfx. There are two DMA engines (SDMA0, SDMA1)
363 * sdma_v2_4_gfx_stop - stop the gfx async dma engines
393 * sdma_v2_4_rlc_stop - stop the compute async dma engines
405 * sdma_v2_4_enable - stop the async dma engines
410 * Halt or unhalt the async dma engines (VI).
433 * sdma_v2_4_gfx_resume - setup and start the async dma engines
521 * sdma_v2_4_rlc_resume - setup and start the async dma engines
571 * sdma_v2_4_start - setup and start the async dma engines
575 * Set up the DMA engines and enable them (VI).
H A Dsdma_v3_0.c142 * DMA engines. These engines are used for compute
143 * and gfx. There are two DMA engines (SDMA0, SDMA1)
474 * sdma_v3_0_gfx_stop - stop the gfx async dma engines
504 * sdma_v3_0_rlc_stop - stop the compute async dma engines
516 * sdma_v3_0_ctx_switch_enable - stop the async dma engines context switch
521 * Halt or unhalt the async dma engines context switch (VI).
541 * sdma_v3_0_enable - stop the async dma engines
546 * Halt or unhalt the async dma engines (VI).
569 * sdma_v3_0_gfx_resume - setup and start the async dma engines
669 * sdma_v3_0_rlc_resume - setup and start the async dma engines
719 * sdma_v3_0_start - setup and start the async dma engines
723 * Set up the DMA engines and enable them (VI).
H A Damdgpu_ib.c113 * On SI, there are two parallel engines fed from the primary ring,
H A Damdgpu_ring.c38 * Most engines on the GPU are fed via ring buffers. Ring
H A Dvi.c894 /* XXX other engines? */ vi_gpu_pci_config_reset()
H A Dcik.c1401 /* XXX other engines? */ cik_gpu_pci_config_reset()
H A Dgfx_v7_0.c1910 * @se_num: number of SEs (shader engines) for the asic
1941 * @se_num: number of SEs (shader engines) for the asic
/linux-4.4.14/drivers/staging/rdma/hfi1/
H A Dsdma.c82 MODULE_PARM_DESC(num_sdma, "Set max number SDMA engines to use");
339 * sdma_wait() - wait for packet egress to complete for all SDMA engines,
849 * distribution of engines per VL.
852 * engines. Any extra engines are added from the last VL on down.
912 /* assign engines */ sdma_map_init()
1003 * sdma_init initializes the specified number of engines.
1046 dd_dev_info(dd, "SDMA engines %zu descq_cnt %u\n", sdma_init()
1049 /* alloc memory for array of send engines */ sdma_init()
1195 * This routine moves all engines to the running state.
1202 /* move all engines to running */ sdma_all_running()
1213 * This routine moves all engines to the idle state.
1220 /* idle all engines */ sdma_all_idle()
1228 * sdma_start() - called to kick off state processing for all engines
1232 * sdma engines. Interrupts need to be working at this point.
1240 /* kick off the engines state processing */ sdma_start()
2680 * SW initiated halt does not perform engines __sdma_process_event()
2997 * SPC freeze handling for SDMA engines. Called when the driver knows
3013 /* tell all engines to stop running and wait */ sdma_freeze_notify()
3017 /* sdma_freeze() will wait for all engines to have stopped */ sdma_freeze_notify()
3021 * SPC freeze handling for SDMA engines. Called when the driver knows
3030 * Make sure all engines have moved out of the running state before sdma_freeze()
3042 /* tell all engines that the SPC is frozen, they can start cleaning */ sdma_freeze()
3057 * SPC freeze handling for the SDMA engines. Called after the SPC is unfrozen.
3068 /* tell all engines start freeze clean up */ sdma_unfreeze()
H A Dsdma.h289 * CSRs for the desired number of SDMA engines.
291 * sdma_start() is used to kick the SDMA engines initialized
1004 * Since the mapping now allows for non-uniform engines per vl, the
1005 * number of engines for a vl is either the vl_engines[vl] or
1016 * For the case where n > nactual, the engines are assigned
1065 * @sde - array of engines for this vl
H A Dhfi.h811 /* fields common to all SDMA engines */
827 /* array of engines sized by num_sdma */
H A Dinit.c1437 * clear dma engines, etc. remove_one()
H A Dchip.c3212 /* notify all SDMA engines that they are going into a freeze */ start_freeze_handling()
6225 /* Now we have to do the same thing for the sdma engines */ set_lidlmc()
6598 /* tell all engines to go running */ set_link_state()
7489 * engines to drop to 0.
9079 * 1 general, "slow path" interrupt (includes the SDMA engines set_up_interrupts()
9872 /* disable send contexts and SDMA engines */ init_chip()
10554 /* insure num_vls isn't larger than number of sdma engines */ hfi1_init_dd()
/linux-4.4.14/arch/arm/plat-iop/
H A Dadma.c2 * platform device definitions for the iop3xx dma/xor engines
/linux-4.4.14/drivers/net/ethernet/stmicro/stmmac/
H A Dnorm_desc.c210 /* The type-1 checksum offload engines append the checksum at ndesc_get_rx_frame_len()
214 * engines. */ ndesc_get_rx_frame_len()
H A Denh_desc.c328 /* The type-1 checksum offload engines append the checksum at enh_desc_get_rx_frame_len()
332 * engines. */ enh_desc_get_rx_frame_len()
/linux-4.4.14/drivers/crypto/qat/qat_common/
H A Dadf_accel_engine.c130 "qat_dev%d started %d acceleration engines\n", adf_ae_start()
151 "qat_dev%d stopped %d acceleration engines\n", adf_ae_stop()
/linux-4.4.14/arch/tile/include/gxio/
H A Dtrio.h89 * for larger transactions; they use specialized hardware engines to
106 * The TRIO push and pull DMA engines allow users to copy blocks of
110 * memory. The DMA engines are managed via an API that is very
/linux-4.4.14/drivers/net/wireless/brcm80211/brcmsmac/
H A Ddma.h29 * support two DMA engines: 32 bits address or 64 bit addressing
H A Dmain.c2017 /* reset the dma engines except first time thru */ brcms_b_corereset()
3341 /* init the tx dma engines */ brcms_b_coreinit()
/linux-4.4.14/drivers/net/ethernet/cavium/liquidio/
H A Dcn68xx_device.c55 /* Prevent service of instruction queue for all DMA engines lio_cn68xx_set_dpi_regs()
/linux-4.4.14/arch/mips/include/asm/mach-pmcs-msp71xx/
H A Dmsp_prom.h119 #define ZSP_TRIAD 'T' /* two TRIAD zsp engines */
/linux-4.4.14/drivers/ata/
H A Dsata_sx4.c38 engine, DIMM memory, and four ATA engines (one per SATA port).
40 handing off to one (or more) of the ATA engines. The ATA
41 engines operate solely on DIMM memory.
858 /* FIXME: if all 4 ATA engines are stopped, also stop HDMA engine */ pdc_freeze()
872 /* FIXME: start HDMA engine, if zero ATA engines running */ pdc_thaw()
H A Dacard-ahci.c399 /* engage engines, captain */ acard_ahci_port_start()
H A Dlibahci.c2369 /* engage engines, captain */ ahci_port_start()
H A Dsata_mv.c1861 * The bmdma engines cannot handle speculative data sizes
/linux-4.4.14/drivers/net/ethernet/micrel/
H A Dks8695net.c640 "Timeout waiting for DMA engines to reset\n"); ks8695_reset()
645 * the engines ks8695_reset()
749 * This routine fills the RX ring, initialises the DMA engines,
751 * engines.
761 /* Initialise the DMA engines */ ks8695_init_net()
1242 * DMA engines and starts the TX queue for a KS8695 ethernet
/linux-4.4.14/arch/arm/include/asm/hardware/
H A Dsa1111.h37 * Use these when feeding target addresses to the DMA engines.
45 * Don't ask the (SAC) DMA engines to move less than this amount.
/linux-4.4.14/include/sound/
H A Dhda_register.h185 /* _X_ = dma engine # and cannot * exceed 29 (per spec max 30 dma engines) */
/linux-4.4.14/arch/powerpc/kernel/
H A Didle_6xx.S92 * L2 prefetch engines are idle. As explained by errata
H A Dl2cr_6xx.S160 * L2 prefetch engines are idle. As explained by errata
/linux-4.4.14/arch/arm/mach-sa1100/
H A Dgeneric.c415 * If the system is going to use the SA-1111 DMA engines, set up
/linux-4.4.14/drivers/gpu/drm/via/
H A Dvia_dmablit.c476 * Rerun handler to delete timer if engines are off, and via_dmablit_timer()
537 * Init all blit engines. Currently we use two, but some hardware have 4.
/linux-4.4.14/drivers/net/wireless/b43legacy/
H A Db43legacy.h696 /* DMA engines. */
698 /* PIO engines. */
/linux-4.4.14/drivers/gpu/drm/amd/include/
H A Dcgs_common.h420 * into account as the requested engines are powered up. When the
421 * request is inactive, the engines may be powered down and clocks may
H A Datombios.h3285 // = 3-7 Reserved for future I2C engines
/linux-4.4.14/drivers/spi/
H A Dspi-bitbang.c339 * (which takes better advantage of hardware like fifos or DMA engines).
/linux-4.4.14/drivers/video/fbdev/sis/
H A Dsis_accel.h271 bit 31 = 1: All engines idle and all queues empty
H A Dsis_main.c3449 /* Check if MMIO and engines are enabled, sisfb_check_engine_and_sync()
3461 * enough to know that the engines sisfb_check_engine_and_sync()
3865 /* Eventually sync engines */ sisfb_post_setmode()
3868 /* (Re-)Initialize chip engines */ sisfb_post_setmode()
/linux-4.4.14/drivers/net/wireless/brcm80211/brcmfmac/
H A Dsdio.h266 u32 PAD[128]; /* DMA engines */
/linux-4.4.14/drivers/net/wireless/ath/ath10k/
H A Dce.h34 * how to use copy engines.
/linux-4.4.14/drivers/crypto/qat/qat_dh895xcc/
H A Dadf_drv.c271 /* If the device has no acceleration engines then ignore it. */ adf_probe()
/linux-4.4.14/include/linux/qed/
H A Dcommon_hsi.h31 #define MAX_NUM_OF_PFS_IN_CHIP (16) /* On both engines */
/linux-4.4.14/arch/ia64/sn/kernel/
H A Dbte.c429 * Indicate that all the block transfer engines on this node bte_init_node()
/linux-4.4.14/drivers/crypto/
H A Dpicoxcell_crypto.c244 * Load a context into the engines context memory.
289 * for passing to the crypto engines. This also DMA maps the data so that the
290 * crypto engines can DMA to/from them.
H A Dhifn_795x.c1011 /* Switch the engines to the PLL */ hifn_init_pll()
/linux-4.4.14/drivers/tty/serial/8250/
H A D8250_dw.c248 * channel on platforms that have DMA engines, but don't have any channels
/linux-4.4.14/drivers/video/fbdev/i810/
H A Di810_accel.c83 * wait_for_engine_idle - waits for all hardware engines to finish
/linux-4.4.14/drivers/gpu/drm/nouveau/nvkm/subdev/clk/
H A Dgt215.c309 /* halt and idle execution engines */ gt215_clk_pre()
/linux-4.4.14/drivers/dma/ioat/
H A Ddma.h166 * @txd: the generic software descriptor for all engines
/linux-4.4.14/drivers/edac/
H A Dedac_core.h106 * DMA engines
/linux-4.4.14/arch/powerpc/include/asm/
H A Dpasemi_dma.h531 /* Routines to allocate function engines */
/linux-4.4.14/drivers/md/
H A Draid5.h136 * api to (optionally) offload operations to dedicated hardware engines.
144 * from starting while a check is in progress. Some dma engines can perform
/linux-4.4.14/drivers/media/platform/omap3isp/
H A Dispstat.c389 * The first case (for the AEWB and AF engines) passes the ISP device, resulting
637 * isp_stat_pcr_enable - Disables/Enables statistic engines.
/linux-4.4.14/drivers/dma/
H A Dmv_xor.c1185 * of engines and channels so that we take into account this mv_xor_probe()
1187 * separate engines when possible. mv_xor_probe()
H A Diop-adma.c17 * This driver supports the asynchrounous DMA copy and RAID engines available
/linux-4.4.14/drivers/bus/
H A Dmvebu-mbus.c163 * actually all devices except the crypto engines.
171 * device. This is the case for the crypto engines.
/linux-4.4.14/drivers/net/ethernet/nvidia/
H A Dforcedeth.c3037 /* stop engines */ nv_change_mtu()
4119 /* stop engines */ nv_do_nic_poll()
4371 /* stop engines */ nv_set_settings()
4530 /* stop engines */ nv_nway_reset()
4629 /* stop engines */ nv_set_ringparam()
4673 /* restart engines */ nv_set_ringparam()
4716 /* stop engines */ nv_set_pauseparam()
5139 /* stop engines */ nv_loopback_test()
5180 /* stop engines */ nv_self_test()
/linux-4.4.14/drivers/scsi/mvsas/
H A Dmv_64xx.c402 /* ladies and gentlemen, start your engines */ mvs_64xx_init()
H A Dmv_94xx.c498 /* ladies and gentlemen, start your engines */ mvs_94xx_init()
/linux-4.4.14/drivers/gpu/drm/nouveau/nvkm/engine/gr/
H A Dnv50.c591 /* MP: CUDA execution engines. */ nv50_gr_trap_handler()
/linux-4.4.14/drivers/char/
H A Dmbcs.c695 /* arm status regs and clear engines */ mbcs_hw_init()
/linux-4.4.14/sound/soc/intel/skylake/
H A Dskl-messages.c830 * DMA engines and releases resources
/linux-4.4.14/drivers/net/usb/
H A Dsmsc95xx.c624 /* Enable or disable Tx & Rx checksum offload engines */ smsc95xx_set_features()
1047 /* Enable or disable checksum offload engines */ smsc95xx_reset()
H A Dsmsc75xx.c1256 /* Enable or disable checksum offload engines */ smsc75xx_reset()
H A Dlan78xx.c1891 /* Enable or disable checksum offload engines */ lan78xx_reset()
/linux-4.4.14/drivers/net/wireless/b43/
H A Db43.h847 /* DMA engines. */
849 /* PIO engines. */
/linux-4.4.14/drivers/gpu/drm/i915/
H A Dintel_lrc.c2133 * This function inits the engines for an Execlists submission style (the equivalent in the
2135 * those engines that are present in the hardware.
2447 * This function can be called more than once, with different engines, if we plan
H A Di915_gem.c3190 * between engines inside the GPU. We only allow one engine to write
H A Di915_irq.c1016 * this we need to combine both engines into our activity counter. vlv_c0_above()
/linux-4.4.14/drivers/tty/serial/
H A Dmpsc.c30 * transmit and receive "engines" going (i.e., indicate data has been
1217 * handling those descriptors, we restart the Rx/Tx engines if they're stopped.
/linux-4.4.14/drivers/input/touchscreen/
H A Dsur40.c644 * minimum number: many DMA engines need a minimum of 2 buffers in the
/linux-4.4.14/drivers/net/ethernet/qlogic/qed/
H A Dqed_main.c843 /* RoCE uses single engine and CMT uses two engines. When using both qed_sb_init()
H A Dqed_hsi.h451 ENGX2_PORTX1 /* 2 engines x 1 port */,
452 ENGX2_PORTX2 /* 2 engines x 2 ports */,
/linux-4.4.14/drivers/gpu/drm/gma500/
H A Dcdv_intel_display.c216 /* Unlike most Intel display engines, on Cedarview the DPLL registers
/linux-4.4.14/Documentation/video4linux/
H A Dv4l2-pci-skeleton.c163 * minimum number: many DMA engines need a minimum of 2 buffers in the
/linux-4.4.14/include/uapi/drm/
H A Di915_drm.h835 * Special GPU caching mode which is coherent with the scanout engines.
H A Dradeon_drm.h1011 /* max shader engines (SE) - needed for geometry shaders, etc. */
/linux-4.4.14/net/netlabel/
H A Dnetlabel_kapi.c1155 * function should only be used by protocol engines, not LSMs. Returns a
/linux-4.4.14/sound/isa/sb/
H A Demu8000.c190 /* turn off envelope engines */ init_audio()
/linux-4.4.14/drivers/scsi/qla2xxx/
H A Dqla_mr.c537 /* stop the XOR DMA engines */ qlafx00_soc_cpu_reset()
543 /* stop the IDMA engines */ qlafx00_soc_cpu_reset()
H A Dqla_nx.c1308 /* Clear all protocol processing engines */ qla82xx_pinit_from_rom()
/linux-4.4.14/drivers/scsi/isci/
H A Dregisters.h478 * engine group that you would also reset all of the protocol engines */
H A Dhost.c2204 /* Initialize hardware PCI Relaxed ordering in DMA engines */ sci_controller_initialize()
/linux-4.4.14/drivers/ide/
H A Dhpt366.c1130 * Reset the state engines. init_chipset_hpt366()
/linux-4.4.14/drivers/vme/bridges/
H A Dvme_ca91cx42.c1744 /* Add dma engines to list */ ca91cx42_probe()
H A Dvme_tsi148.c2444 /* Add dma engines to list */ tsi148_probe()
/linux-4.4.14/drivers/usb/musb/
H A Dmusb_gadget.c507 * engines might handle this by themselves. musb_g_tx()
/linux-4.4.14/drivers/infiniband/hw/qib/
H A Dqib_init.c1563 * clear dma engines, etc. qib_remove_one()
/linux-4.4.14/drivers/gpu/drm/nouveau/nvkm/engine/device/
H A Dbase.c2334 /* identify the chipset, and determine classes of subdev/engines */
/linux-4.4.14/drivers/net/ethernet/natsemi/
H A Dnatsemi.c2542 /* stop engines */ natsemi_change_mtu()
2550 /* restart engines */ natsemi_change_mtu()
/linux-4.4.14/drivers/usb/host/
H A Disp1362-hcd.c2066 * DMA engines that care about alignment (PXA) isp1362_show()
/linux-4.4.14/drivers/usb/misc/sisusbvga/
H A Dsisusb.c1915 SETIREG(SISSR, 0x20, 0xa1); /* enable engines */ sisusb_set_default_mode()
/linux-4.4.14/drivers/scsi/qla4xxx/
H A Dql4_nx.c1167 /* Clear all protocol processing engines */ qla4_82xx_pinit_from_rom()
/linux-4.4.14/drivers/net/ethernet/intel/ixgbe/
H A Dixgbe_ethtool.c1642 /* shut down the DMA engines now so they can be reinitialized later */ ixgbe_free_desc_rings()
/linux-4.4.14/drivers/net/ethernet/sun/
H A Dsungem.c2068 /* Init DMA & MAC engines */ gem_reinit_chip()
H A Dcassini.c3810 /* disable dma engines. */ cas_reset()
H A Dcassini.h709 /* current state of RX DMA state engines + other info
/linux-4.4.14/drivers/net/ethernet/tehuti/
H A Dtehuti.c388 * bdx_hw_start - inits registers and starts HW's Rx and Tx engines
/linux-4.4.14/drivers/net/ethernet/packetengines/
H A Dhamachi.c1874 * TODO: Shut down the Rx and Tx engines while doing this. netdev_ioctl()
/linux-4.4.14/drivers/net/ethernet/sfc/
H A Defx.c2516 * engines are not restarted, pending a RESET_DISABLE. */ efx_reset_up()
/linux-4.4.14/drivers/net/ethernet/freescale/
H A Ducc_geth.c2182 /* read the number of risc engines, update the riscTx and riscRx ucc_struct_init()
/linux-4.4.14/drivers/mtd/nand/
H A Dnand_base.c1180 * different from the NAND page size. When fixing bitflips, ECC engines will
/linux-4.4.14/drivers/net/ethernet/agere/
H A Det131x.c386 * TXdma and Rxdma engines
/linux-4.4.14/drivers/net/ethernet/broadcom/bnx2x/
H A Dbnx2x_main.c1760 * belongs to. Currently only only 2 engines is supported.
4362 * 20 - Chip reset flow bit. When set none-leader must wait for both engines
/linux-4.4.14/drivers/net/ethernet/marvell/
H A Dmvpp2.c3337 /* Disable classification engines */ mvpp2_cls_port_config()
/linux-4.4.14/drivers/scsi/aic7xxx/
H A Daic79xx_core.c8763 * Safely shut down our DMA engines. Always start with ahd_reset_channel()

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