Searched refs:divsel (Results 1 - 3 of 3) sorted by relevance
| /linux-4.4.14/drivers/mfd/ |
| H A D | db8500-prcmu.c | 504 u32 divsel; member in struct:dsiclk
511 .divsel = PRCM_DSI_PLLOUT_SEL_PHI,
516 .divsel = PRCM_DSI_PLLOUT_SEL_PHI,
1446 val |= ((enable ? dsiclk[n].divsel : PRCM_DSI_PLLOUT_SEL_OFF) << request_dsiclk()
1600 u32 divsel; dsiclk_rate() local
1603 divsel = readl(PRCM_DSI_PLLOUT_SEL); dsiclk_rate()
1604 divsel = ((divsel & dsiclk[n].divsel_mask) >> dsiclk[n].divsel_shift); dsiclk_rate()
1606 if (divsel == PRCM_DSI_PLLOUT_SEL_OFF) dsiclk_rate()
1607 divsel = dsiclk[n].divsel; dsiclk_rate()
1609 dsiclk[n].divsel = divsel; dsiclk_rate()
1611 switch (divsel) { dsiclk_rate()
1950 dsiclk[n].divsel = (div == 1) ? PRCM_DSI_PLLOUT_SEL_PHI : set_dsiclk_rate()
1956 val |= (dsiclk[n].divsel << dsiclk[n].divsel_shift); set_dsiclk_rate()
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| /linux-4.4.14/sound/soc/codecs/ |
| H A D | wm9713.c | 713 u32 divsel:1; member in struct:_pll_div
736 pll_div->divsel = 1; pll_factors()
745 pll_div->divsel = 0; pll_factors()
808 (pll_div.divsel << 9) | (pll_div.divctl << 8); wm9713_set_pll()
813 (pll_div.divsel << 9) | (pll_div.divctl << 8); wm9713_set_pll()
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| /linux-4.4.14/drivers/gpu/drm/i915/ |
| H A D | intel_display.c | 3987 u32 divsel, phaseinc, auxdiv, phasedir = 0; lpt_program_iclkip() local
4006 divsel = 0x41; lpt_program_iclkip()
4024 divsel = msb_divisor_value - 2; lpt_program_iclkip()
4029 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) & lpt_program_iclkip()
4034 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n", lpt_program_iclkip()
4037 divsel, lpt_program_iclkip()
4044 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel); lpt_program_iclkip()
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