Searched refs:ddr_pll (Results 1 - 4 of 4) sorted by relevance
| /linux-4.4.14/arch/mips/ath79/ |
| H A D | clock.c | 248 u32 cpu_pll, ddr_pll; ar934x_clocks_init() local
311 ddr_pll = ar934x_get_pll_freq(ref_rate, ref_div, nint, ar934x_clocks_init()
324 cpu_rate = ddr_pll / (postdiv + 1); ar934x_clocks_init()
332 ddr_rate = ddr_pll / (postdiv + 1); ar934x_clocks_init()
342 ahb_rate = ddr_pll / (postdiv + 1); ar934x_clocks_init()
364 u32 cpu_pll, ddr_pll; qca955x_clocks_init() local
397 ddr_pll = nint * ref_rate / ref_div; qca955x_clocks_init()
398 ddr_pll += frac * ref_rate / (ref_div * (1 << 10)); qca955x_clocks_init()
399 ddr_pll /= (1 << out_div); qca955x_clocks_init()
409 cpu_rate = ddr_pll / (postdiv + 1); qca955x_clocks_init()
421 ddr_rate = ddr_pll / (postdiv + 1); qca955x_clocks_init()
429 ahb_rate = ddr_pll / (postdiv + 1); qca955x_clocks_init()
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| /linux-4.4.14/drivers/clk/ux500/ |
| H A D | u8540_clk.c | 66 clk = clk_reg_prcmu_gate("ddr_pll", NULL, PRCMU_PLLDDR, u8540_clk_init()
68 clk_register_clkdev(clk, "ddr_pll", NULL); u8540_clk_init()
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| H A D | u8500_of_clk.c | 101 clk = clk_reg_prcmu_gate("ddr_pll", NULL, PRCMU_PLLDDR, u8500_clk_init()
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| /linux-4.4.14/drivers/clk/ti/ |
| H A D | fapll.c | 45 /* The bypass bit is inverted on the ddr_pll.. */
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