| /linux-4.4.14/drivers/crypto/qat/qat_common/ |
| H A D | adf_hw_arbiter.c | 62 #define WRITE_CSR_ARB_RINGSRVARBEN(csr_addr, index, value) \
63 ADF_CSR_WR(csr_addr, ADF_ARB_RINGSRVARBEN_OFFSET + \
66 #define WRITE_CSR_ARB_RESPORDERING(csr_addr, index, value) \
67 ADF_CSR_WR(csr_addr, (ADF_ARB_OFFSET + \
70 #define WRITE_CSR_ARB_WEIGHT(csr_addr, arb, index, value) \
71 ADF_CSR_WR(csr_addr, (ADF_ARB_OFFSET + \
75 #define WRITE_CSR_ARB_SARCONFIG(csr_addr, index, value) \
76 ADF_CSR_WR(csr_addr, ADF_ARB_OFFSET + \
79 #define WRITE_CSR_ARB_WRK_2_SER_MAP(csr_addr, index, value) \
80 ADF_CSR_WR(csr_addr, (ADF_ARB_OFFSET + \
84 #define WRITE_CSR_ARB_WQCFG(csr_addr, index, value) \
85 ADF_CSR_WR(csr_addr, (ADF_ARB_OFFSET + \
91 void __iomem *csr = accel_dev->transport->banks[0].csr_addr; adf_init_arb()
135 WRITE_CSR_ARB_RINGSRVARBEN(ring->bank->csr_addr, adf_update_ring_arb()
150 csr = accel_dev->transport->banks[0].csr_addr; adf_exit_arb()
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| H A D | adf_transport.c | 104 WRITE_CSR_INT_COL_EN(bank->csr_addr, bank->bank_number, bank->irq_mask); adf_enable_ring_irq()
105 WRITE_CSR_INT_COL_CTL(bank->csr_addr, bank->bank_number, adf_enable_ring_irq()
114 WRITE_CSR_INT_COL_EN(bank->csr_addr, bank->bank_number, bank->irq_mask); adf_disable_ring_irq()
131 WRITE_CSR_RING_TAIL(ring->bank->csr_addr, ring->bank->bank_number, adf_send_message()
152 WRITE_CSR_RING_HEAD(ring->bank->csr_addr, adf_handle_response()
164 WRITE_CSR_RING_CONFIG(ring->bank->csr_addr, ring->bank->bank_number, adf_configure_tx_ring()
175 WRITE_CSR_RING_CONFIG(ring->bank->csr_addr, ring->bank->bank_number, adf_configure_rx_ring()
211 WRITE_CSR_RING_BASE(ring->bank->csr_addr, ring->bank->bank_number, adf_init_ring()
321 WRITE_CSR_RING_CONFIG(bank->csr_addr, bank->bank_number, adf_remove_ring()
323 WRITE_CSR_RING_BASE(bank->csr_addr, bank->bank_number, adf_remove_ring()
336 empty_rings = READ_CSR_E_STAT(bank->csr_addr, bank->bank_number); adf_ring_response_handler()
362 WRITE_CSR_INT_FLAG_AND_COL(bank->csr_addr, bank->bank_number, adf_response_handler()
400 uint32_t bank_num, void __iomem *csr_addr) adf_init_bank()
409 bank->csr_addr = csr_addr; adf_init_bank()
424 WRITE_CSR_RING_CONFIG(csr_addr, bank_num, i, 0); adf_init_bank()
425 WRITE_CSR_RING_BASE(csr_addr, bank_num, i, 0); adf_init_bank()
450 WRITE_CSR_INT_SRCSEL(csr_addr, bank_num); adf_init_bank()
475 void __iomem *csr_addr; adf_init_etr_data() local
496 csr_addr = accel_dev->accel_pci_dev.pci_bars[i].virt_addr; adf_init_etr_data()
510 csr_addr); adf_init_etr_data()
398 adf_init_bank(struct adf_accel_dev *accel_dev, struct adf_etr_bank_data *bank, uint32_t bank_num, void __iomem *csr_addr) adf_init_bank() argument
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| H A D | adf_transport_debug.c | 89 void __iomem *csr = ring->bank->csr_addr; adf_ring_show()
214 void __iomem *csr = bank->csr_addr; adf_bank_show()
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| H A D | adf_transport_internal.h | 78 void __iomem *csr_addr; member in struct:adf_etr_bank_data
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| H A D | qat_hal.c | 443 void __iomem *csr_addr = handle->hal_ep_csr_addr_v + qat_hal_init_esram() local
447 csr_val = ADF_CSR_RD(csr_addr, 0); qat_hal_init_esram()
451 csr_val = ADF_CSR_RD(csr_addr, 0); qat_hal_init_esram()
453 ADF_CSR_WR(csr_addr, 0, csr_val); qat_hal_init_esram()
457 csr_val = ADF_CSR_RD(csr_addr, 0); qat_hal_init_esram()
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| /linux-4.4.14/arch/mips/include/asm/octeon/ |
| H A D | cvmx.h | 264 static inline void cvmx_write_csr(uint64_t csr_addr, uint64_t val) cvmx_write_csr() argument
266 cvmx_write64(csr_addr, val); cvmx_write_csr()
274 if (((csr_addr >> 40) & 0x7ffff) == (0x118)) cvmx_write_csr()
284 static inline uint64_t cvmx_read_csr(uint64_t csr_addr) cvmx_read_csr() argument
286 uint64_t val = cvmx_read64(csr_addr); cvmx_read_csr()
297 static inline void cvmx_read_csr_async(uint64_t scraddr, uint64_t csr_addr) cvmx_read_csr_async() argument
307 addr.u64 = csr_addr; cvmx_read_csr_async()
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| H A D | octeon-model.h | 309 static inline uint64_t cvmx_read_csr(uint64_t csr_addr);
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| /linux-4.4.14/drivers/crypto/qat/qat_dh895xccvf/ |
| H A D | adf_isr.c | 181 WRITE_CSR_INT_FLAG_AND_COL(bank->csr_addr, bank->bank_number, adf_isr()
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| /linux-4.4.14/drivers/crypto/qat/qat_dh895xcc/ |
| H A D | adf_isr.c | 100 WRITE_CSR_INT_FLAG_AND_COL(bank->csr_addr, bank->bank_number, 0); adf_msix_isr_bundle()
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