Searched refs:csr0 (Results 1 - 17 of 17) sorted by relevance

/linux-4.4.14/drivers/net/ethernet/amd/
H A Dariadne.c244 int csr0, boguscnt; ariadne_interrupt() local
255 while ((csr0 = lance->RDP) & (ERR | RINT | TINT) && --boguscnt >= 0) { ariadne_interrupt()
257 lance->RDP = csr0 & ~(INEA | TDMD | STOP | STRT | INIT); ariadne_interrupt()
261 netdev_dbg(dev, "interrupt csr0=%#02x new csr=%#02x [", ariadne_interrupt()
262 csr0, lance->RDP); ariadne_interrupt()
263 if (csr0 & INTR) ariadne_interrupt()
265 if (csr0 & INEA) ariadne_interrupt()
267 if (csr0 & RXON) ariadne_interrupt()
269 if (csr0 & TXON) ariadne_interrupt()
271 if (csr0 & TDMD) ariadne_interrupt()
273 if (csr0 & STOP) ariadne_interrupt()
275 if (csr0 & STRT) ariadne_interrupt()
277 if (csr0 & INIT) ariadne_interrupt()
279 if (csr0 & ERR) ariadne_interrupt()
281 if (csr0 & BABL) ariadne_interrupt()
283 if (csr0 & CERR) ariadne_interrupt()
285 if (csr0 & MISS) ariadne_interrupt()
287 if (csr0 & MERR) ariadne_interrupt()
289 if (csr0 & RINT) ariadne_interrupt()
291 if (csr0 & TINT) ariadne_interrupt()
293 if (csr0 & IDON) ariadne_interrupt()
299 if (csr0 & RINT) { /* Rx interrupt */ ariadne_interrupt()
304 if (csr0 & TINT) { /* Tx-done interrupt */ ariadne_interrupt()
332 csr0); ariadne_interrupt()
364 if (csr0 & BABL) { ariadne_interrupt()
368 if (csr0 & MISS) { ariadne_interrupt()
372 if (csr0 & MERR) { ariadne_interrupt()
375 csr0); ariadne_interrupt()
555 netdev_dbg(dev, "%s: csr0 %04x\n", __func__, lance->RDP); ariadne_start_xmit()
H A Dni65.c726 int csr0 = CSR0_INEA; ni65_stop_start() local
766 writedatareg(CSR0_STRT | csr0); ni65_stop_start()
775 writedatareg(CSR0_TDMD | CSR0_INEA | csr0); ni65_stop_start()
788 writedatareg(CSR0_STRT | csr0); ni65_stop_start()
878 int csr0 = 0; ni65_interrupt() local
888 csr0 = inw(PORT+L_DATAREG); ni65_interrupt()
891 writedatareg( (csr0 & CSR0_CLRALL) ); /* ack interrupts, disable int. */ ni65_interrupt()
893 writedatareg( (csr0 & CSR0_CLRALL) | CSR0_INEA ); /* ack interrupts, interrupts enabled */ ni65_interrupt()
896 if(!(csr0 & (CSR0_ERR | CSR0_RINT | CSR0_TINT))) ni65_interrupt()
899 if(csr0 & CSR0_RINT) /* RECV-int? */ ni65_interrupt()
900 ni65_recv_intr(dev,csr0); ni65_interrupt()
901 if(csr0 & CSR0_TINT) /* XMIT-int? */ ni65_interrupt()
902 ni65_xmit_intr(dev,csr0); ni65_interrupt()
904 if(csr0 & CSR0_ERR) ni65_interrupt()
907 printk(KERN_ERR "%s: general error: %04x.\n",dev->name,csr0); ni65_interrupt()
908 if(csr0 & CSR0_BABL) ni65_interrupt()
910 if(csr0 & CSR0_MISS) { ni65_interrupt()
917 if(csr0 & CSR0_MERR) { ni65_interrupt()
919 printk(KERN_ERR "%s: Ooops .. memory error: %04x.\n",dev->name,csr0); ni65_interrupt()
960 ni65_recv_intr(dev,csr0); ni65_interrupt()
970 if( (csr0 & (CSR0_RXON | CSR0_TXON)) != (CSR0_RXON | CSR0_TXON) ) { ni65_interrupt()
985 static void ni65_xmit_intr(struct net_device *dev,int csr0) ni65_xmit_intr() argument
1022 printk(KERN_ERR "%s: xmit-error: %04x %02x-%04x\n",dev->name,csr0,(int) tmdstat,(int) tmdp->status2); ni65_xmit_intr()
1023 if(!(csr0 & CSR0_BABL)) /* don't count errors twice */ ni65_xmit_intr()
1049 static void ni65_recv_intr(struct net_device *dev,int csr0) ni65_recv_intr() argument
1072 dev->name,(int) rmdstat,csr0,(int) inw(PORT+L_DATAREG) ); ni65_recv_intr()
1082 if(!(csr0 & CSR0_MISS)) /* don't count errors twice */ ni65_recv_intr()
H A D7990.c129 /* Point back to csr0 */ load_csrs()
241 printk("LANCE unopened after %d ticks, csr0=%4.4x.\n", i, READRDP(lp)); init_restart_lance()
362 /* csr0 is 2f3 */ lance_tx()
364 /* csr0 is 73 */ lance_tx()
444 int csr0; lance_interrupt() local
449 csr0 = READRDP(lp); lance_interrupt()
453 if (!(csr0 & LE_C0_INTR)) { /* Check if any interrupt has */ lance_interrupt()
459 WRITERDP(lp, csr0 & ~(LE_C0_INEA|LE_C0_TDMD|LE_C0_STOP|LE_C0_STRT|LE_C0_INIT)); lance_interrupt()
461 if ((csr0 & LE_C0_ERR)) { lance_interrupt()
466 if (csr0 & LE_C0_RINT) lance_interrupt()
469 if (csr0 & LE_C0_TINT) lance_interrupt()
473 if (csr0 & LE_C0_BABL) lance_interrupt()
475 if (csr0 & LE_C0_MISS) lance_interrupt()
477 if (csr0 & LE_C0_MERR) { lance_interrupt()
479 dev->name, csr0); lance_interrupt()
H A Da2065.c144 /* Point back to csr0 */ load_csrs()
233 pr_err("unopened after %d ticks, csr0=%04x\n", i, ll->rdp); init_restart_lance()
332 /* csr0 is 2f3 */ lance_tx()
334 /* csr0 is 73 */ lance_tx()
418 int csr0; lance_interrupt() local
421 csr0 = ll->rdp; lance_interrupt()
423 if (!(csr0 & LE_C0_INTR)) /* Check if any interrupt has */ lance_interrupt()
427 ll->rdp = csr0 & ~(LE_C0_INEA | LE_C0_TDMD | LE_C0_STOP | LE_C0_STRT | lance_interrupt()
430 if (csr0 & LE_C0_ERR) { lance_interrupt()
435 if (csr0 & LE_C0_RINT) lance_interrupt()
438 if (csr0 & LE_C0_TINT) lance_interrupt()
442 if (csr0 & LE_C0_BABL) lance_interrupt()
444 if (csr0 & LE_C0_MISS) lance_interrupt()
446 if (csr0 & LE_C0_MERR) { lance_interrupt()
448 csr0); lance_interrupt()
H A Dsun3lance.c436 DPRINTK( 2, ( "lance_open(): opening %s failed, i=%d, csr0=%04x\n", lance_open()
446 DPRINTK( 2, ( "%s: LANCE is open, csr0 %04x\n", dev->name, DREG )); lance_open()
582 DPRINTK( 2, ( "%s: lance_start_xmit() called, csr0 %4.4x.\n", lance_start_xmit()
637 DPRINTK( 2, ( "%s: lance_start_xmit() exiting, csr0 %4.4x.\n", lance_start_xmit()
657 int csr0; lance_interrupt() local
673 csr0 = DREG; lance_interrupt()
676 DREG = csr0 & (CSR0_TINT | CSR0_RINT | CSR0_IDON); lance_interrupt()
679 if(csr0 & CSR0_ERR) lance_interrupt()
683 DPRINTK( 2, ( "%s: interrupt csr0=%04x new csr=%04x.\n", lance_interrupt()
684 dev->name, csr0, DREG )); lance_interrupt()
686 if (csr0 & CSR0_TINT) { /* Tx-done interrupt */ lance_interrupt()
745 if (csr0 & CSR0_RINT) /* Rx interrupt */ lance_interrupt()
749 if (csr0 & CSR0_BABL) dev->stats.tx_errors++; /* Tx babble. */ lance_interrupt()
750 if (csr0 & CSR0_MISS) dev->stats.rx_errors++; /* Missed a Rx frame. */ lance_interrupt()
751 if (csr0 & CSR0_MERR) { lance_interrupt()
753 "status %04x.\n", dev->name, csr0 )); lance_interrupt()
769 DPRINTK(2, ("restarting interrupt, csr0=%#04x\n", DREG)); lance_interrupt()
773 DPRINTK( 2, ( "%s: exiting interrupt, csr0=%#04x.\n", lance_interrupt()
H A Datarilance.c663 DPRINTK( 2, ( "lance_open(): opening %s failed, i=%d, csr0=%04x\n", lance_open()
674 DPRINTK( 2, ( "%s: LANCE is open, csr0 %04x\n", dev->name, DREG )); lance_open()
781 DPRINTK( 2, ( "%s: lance_start_xmit() called, csr0 %4.4x.\n", lance_start_xmit()
854 int csr0, boguscnt = 10; lance_interrupt() local
868 while( ((csr0 = DREG) & (CSR0_ERR | CSR0_TINT | CSR0_RINT)) && lance_interrupt()
872 DREG = csr0 & ~(CSR0_INIT | CSR0_STRT | CSR0_STOP | lance_interrupt()
875 DPRINTK( 2, ( "%s: interrupt csr0=%04x new csr=%04x.\n", lance_interrupt()
876 dev->name, csr0, DREG )); lance_interrupt()
878 if (csr0 & CSR0_RINT) /* Rx interrupt */ lance_interrupt()
881 if (csr0 & CSR0_TINT) { /* Tx-done interrupt */ lance_interrupt()
905 dev->name, csr0 )); lance_interrupt()
939 if (csr0 & CSR0_BABL) dev->stats.tx_errors++; /* Tx babble. */ lance_interrupt()
940 if (csr0 & CSR0_MISS) dev->stats.rx_errors++; /* Missed a Rx frame. */ lance_interrupt()
941 if (csr0 & CSR0_MERR) { lance_interrupt()
943 "status %04x.\n", dev->name, csr0 )); lance_interrupt()
953 DPRINTK( 2, ( "%s: exiting interrupt, csr0=%#04x.\n", lance_interrupt()
H A Ddeclance.c318 /* Point back to csr0 */ load_csrs()
538 printk("LANCE unopened after %d ticks, csr0=%4.4x.\n", init_restart_lance()
543 printk("LANCE unopened after %d ticks, csr0=%4.4x.\n", init_restart_lance()
737 int csr0; lance_interrupt() local
740 csr0 = ll->rdp; lance_interrupt()
743 writereg(&ll->rdp, csr0 & (LE_C0_INTR | LE_C0_TINT | LE_C0_RINT)); lance_interrupt()
745 if ((csr0 & LE_C0_ERR)) { lance_interrupt()
750 if (csr0 & LE_C0_RINT) lance_interrupt()
753 if (csr0 & LE_C0_TINT) lance_interrupt()
756 if (csr0 & LE_C0_BABL) lance_interrupt()
759 if (csr0 & LE_C0_MISS) lance_interrupt()
762 if (csr0 & LE_C0_MERR) { lance_interrupt()
763 printk("%s: Memory error, status %04x\n", dev->name, csr0); lance_interrupt()
H A Dlance.c819 printk("%s: LANCE open after %d ticks, init block %#x csr0 %4.4x.\n", lance_open()
963 printk("%s: lance_start_xmit() called, csr0 %4.4x.\n", dev->name, lance_start_xmit()
1025 int csr0, ioaddr, boguscnt=10; lance_interrupt() local
1034 while ((csr0 = inw(dev->base_addr + LANCE_DATA)) & 0x8600 && lance_interrupt()
1037 outw(csr0 & ~0x004f, dev->base_addr + LANCE_DATA); lance_interrupt()
1042 printk("%s: interrupt csr0=%#2.2x new csr=%#2.2x.\n", lance_interrupt()
1043 dev->name, csr0, inw(dev->base_addr + LANCE_DATA)); lance_interrupt()
1045 if (csr0 & 0x0400) /* Rx interrupt */ lance_interrupt()
1048 if (csr0 & 0x0200) { /* Tx-done interrupt */ lance_interrupt()
1075 dev->name, csr0); lance_interrupt()
1112 if (csr0 & 0x4000) lance_interrupt()
1114 if (csr0 & 0x1000) lance_interrupt()
1116 if (csr0 & 0x0800) { lance_interrupt()
1118 dev->name, csr0); lance_interrupt()
H A Dsunlance.c315 /* Point back to csr0 */ load_csrs()
486 printk(KERN_ERR "LANCE unopened after %d ticks, csr0=%4.4x.\n", init_restart_lance()
818 int csr0; lance_interrupt() local
821 csr0 = sbus_readw(lp->lregs + RDP); lance_interrupt()
824 sbus_writew(csr0 & (LE_C0_INTR | LE_C0_TINT | LE_C0_RINT), lance_interrupt()
827 if ((csr0 & LE_C0_ERR) != 0) { lance_interrupt()
834 if (csr0 & LE_C0_RINT) lance_interrupt()
837 if (csr0 & LE_C0_TINT) lance_interrupt()
840 if (csr0 & LE_C0_BABL) lance_interrupt()
843 if (csr0 & LE_C0_MISS) lance_interrupt()
846 if (csr0 & LE_C0_MERR) { lance_interrupt()
851 dev->name, csr0, addr & 0xffffff); lance_interrupt()
854 dev->name, csr0); lance_interrupt()
H A Dpcnet32.c1384 int i, csr0; pcnet32_get_regs() local
1393 csr0 = a->read_csr(ioaddr, CSR0); pcnet32_get_regs()
1394 if (!(csr0 & CSR0_STOP)) /* If not stopped */ pcnet32_get_regs()
1431 if (!(csr0 & CSR0_STOP)) { /* If not stopped */ pcnet32_get_regs()
2240 "pcnet32 open after %d ticks, init block %#x csr0 %4.4x\n", pcnet32_open()
2447 "%s() called, csr0 %4.4x\n", pcnet32_start_xmit()
2501 u16 csr0; pcnet32_interrupt() local
2509 csr0 = lp->a->read_csr(ioaddr, CSR0); pcnet32_interrupt()
2510 while ((csr0 & 0x8f00) && --boguscnt >= 0) { pcnet32_interrupt()
2511 if (csr0 == 0xffff) pcnet32_interrupt()
2514 lp->a->write_csr(ioaddr, CSR0, csr0 & ~0x004f); pcnet32_interrupt()
2517 "interrupt csr0=%#2.2x new csr=%#2.2x\n", pcnet32_interrupt()
2518 csr0, lp->a->read_csr(ioaddr, CSR0)); pcnet32_interrupt()
2521 if (csr0 & 0x4000) pcnet32_interrupt()
2523 if (csr0 & 0x1000) { pcnet32_interrupt()
2537 if (csr0 & 0x0800) { pcnet32_interrupt()
2539 csr0); pcnet32_interrupt()
2552 csr0 = lp->a->read_csr(ioaddr, CSR0); pcnet32_interrupt()
2556 "exiting interrupt, csr0=%#4.4x\n", pcnet32_interrupt()
/linux-4.4.14/drivers/net/ethernet/dec/tulip/
H A Dtulip_core.c87 static int csr0 = 0x01A00000 | 0xE000; variable
89 static int csr0 = 0x01A00000 | 0x8000; variable
95 static int csr0 = 0x01A00000 | 0x9000; variable
97 static int csr0 = 0x01A00000 | 0x4800; variable
99 static int csr0 = 0x00200000 | 0x4000; variable
101 static int csr0; variable
116 module_param(csr0, int, 0);
325 iowrite32(tp->csr0, ioaddr + CSR0); tulip_up()
1198 u32 csr0; tulip_mwi_config() local
1203 tp->csr0 = csr0 = 0; tulip_mwi_config()
1206 csr0 |= MRM | MWI; tulip_mwi_config()
1215 if ((csr0 & MWI) && (!(pci_command & PCI_COMMAND_INVALIDATE))) tulip_mwi_config()
1216 csr0 &= ~MWI; tulip_mwi_config()
1220 if ((csr0 & MWI) && (cache == 0)) { tulip_mwi_config()
1221 csr0 &= ~MWI; tulip_mwi_config()
1230 csr0 |= MRL | (1 << CALShift) | (16 << BurstLenShift); tulip_mwi_config()
1233 csr0 |= MRL | (2 << CALShift) | (16 << BurstLenShift); tulip_mwi_config()
1236 csr0 |= MRL | (3 << CALShift) | (32 << BurstLenShift); tulip_mwi_config()
1244 * csr0, so save it and exit tulip_mwi_config()
1249 /* we don't have a good csr0 or cache line size, disable MWI */ tulip_mwi_config()
1250 if (csr0 & MWI) { tulip_mwi_config()
1252 csr0 &= ~MWI; tulip_mwi_config()
1258 csr0 |= (8 << BurstLenShift) | (1 << CALShift); tulip_mwi_config()
1261 tp->csr0 = csr0; tulip_mwi_config()
1263 netdev_dbg(dev, "MWI config cacheline=%d, csr0=%08x\n", tulip_mwi_config()
1264 cache, csr0); tulip_mwi_config()
1383 csr0 = MRL | MRM | (8 << BurstLenShift) | (1 << CALShift); tulip_init_one()
1389 if ((csr0 & 0x3f00) == 0) tulip_init_one()
1390 csr0 |= 0x2000; tulip_init_one()
1395 csr0 &= ~0xfff10000; /* zero reserved bits 31:20, 16 */ tulip_init_one()
1399 csr0 &= ~0x01f100ff; tulip_init_one()
1401 csr0 = (csr0 & ~0xff00) | 0xe000; tulip_init_one()
1475 tp->csr0 = csr0; tulip_init_one()
1984 if (!csr0) { tulip_init()
1985 pr_warn("tulip: unknown CPU architecture, using default csr0\n"); tulip_init()
1987 csr0 = 0x00A00000 | 0x4800; tulip_init()
H A Dtulip.h437 unsigned int csr0; /* CSR0 setting. */ member in struct:tulip_private
H A Dde4x5.c827 s32 csr0; /* Saved Bus Mode Register */ member in struct:de4x5_private::__anon6807
3731 lp->cache.csr0 = inl(DE4X5_BMR); de4x5_cache_state()
3737 outl(lp->cache.csr0, DE4X5_BMR); de4x5_cache_state()
H A Dwinbond-840.c910 dev_warn(&dev->dev, "unknown CPU architecture, using default csr0 setting\n"); init_registers()
/linux-4.4.14/drivers/net/wan/
H A Dsbni.c538 unsigned char csr0; handle_channel() local
550 csr0 = inb( ioaddr + CSR0 ); handle_channel()
551 if( ( csr0 & (RC_RDY | TR_RDY) ) == 0 ) handle_channel()
556 if( csr0 & RC_RDY ) handle_channel()
563 csr0 = inb( ioaddr + CSR0 ); handle_channel()
564 if( !(csr0 & TR_RDY) || (csr0 & RC_RDY) ) handle_channel()
1039 unsigned char csr0; sbni_watchdog() local
1043 csr0 = inb( dev->base_addr + CSR0 ); sbni_watchdog()
1044 if( csr0 & RC_CHK ) { sbni_watchdog()
1047 if( csr0 & (RC_RDY | BU_EMP) ) sbni_watchdog()
1057 csr0 = inb( dev->base_addr + CSR0 ); sbni_watchdog()
1062 outb( csr0 | RC_CHK, dev->base_addr + CSR0 ); sbni_watchdog()
1277 unsigned char csr0; sbni_card_probe() local
1279 csr0 = inb( ioaddr + CSR0 ); sbni_card_probe()
1280 if( csr0 != 0xff && csr0 != 0x00 ) { sbni_card_probe()
1281 csr0 &= ~EN_INT; sbni_card_probe()
1282 if( csr0 & BU_EMP ) sbni_card_probe()
1283 csr0 |= EN_INT; sbni_card_probe()
1285 if( VALID_DECODER & (1 << (csr0 >> 4)) ) sbni_card_probe()
/linux-4.4.14/drivers/usb/musb/
H A Dmusb_gadget_ep0.c148 /* fill up the fifo; caller updates csr0 */ service_tx_status_request()
553 dev_dbg(musb->controller, "odd; csr0 %04x\n", musb_readw(regs, MUSB_CSR0)); ep0_txstate()
872 * driver, we know how to wrap this up: csr0 has musb_g_ep0_irq()
H A Dmusb_host.c1150 dev_dbg(musb->controller, "<== csr0 %04x, qh %p, count %d, urb %p, stage %d\n", musb_h_ep0_irq()
1165 dev_dbg(musb->controller, "no response, csr0 %04x\n", csr); musb_h_ep0_irq()

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