Searched refs:clk_mgr_base_addr (Results 1 - 4 of 4) sorted by relevance

/linux-4.4.14/drivers/clk/socfpga/
H A Dclk-gate.c45 l4_src = readl(clk_mgr_base_addr + CLKMGR_L4SRC); socfpga_clk_get_parent()
49 l4_src = readl(clk_mgr_base_addr + CLKMGR_L4SRC); socfpga_clk_get_parent()
53 perpll_src = readl(clk_mgr_base_addr + CLKMGR_PERPLL_SRC); socfpga_clk_get_parent()
70 src_reg = readl(clk_mgr_base_addr + CLKMGR_L4SRC); socfpga_clk_set_parent()
73 writel(src_reg, clk_mgr_base_addr + CLKMGR_L4SRC); socfpga_clk_set_parent()
75 src_reg = readl(clk_mgr_base_addr + CLKMGR_L4SRC); socfpga_clk_set_parent()
78 writel(src_reg, clk_mgr_base_addr + CLKMGR_L4SRC); socfpga_clk_set_parent()
80 src_reg = readl(clk_mgr_base_addr + CLKMGR_PERPLL_SRC); socfpga_clk_set_parent()
92 writel(src_reg, clk_mgr_base_addr + CLKMGR_PERPLL_SRC); socfpga_clk_set_parent()
202 socfpga_clk->hw.reg = clk_mgr_base_addr + clk_gate[0]; __socfpga_gate_init()
217 socfpga_clk->div_reg = clk_mgr_base_addr + div_reg[0]; __socfpga_gate_init()
H A Dclk-pll.c46 void __iomem *clk_mgr_base_addr; variable
57 bypass = readl(clk_mgr_base_addr + CLKMGR_BYPASS); clk_pll_recalc_rate()
102 clk_mgr_base_addr = of_iomap(clkmgr_np, 0); __socfpga_pll_init()
103 BUG_ON(!clk_mgr_base_addr); __socfpga_pll_init()
104 pll_clk->hw.reg = clk_mgr_base_addr + reg; __socfpga_pll_init()
H A Dclk-periph.c51 clk_src = readl(clk_mgr_base_addr + CLKMGR_DBCTRL); clk_periclk_get_parent()
79 periph_clk->hw.reg = clk_mgr_base_addr + reg; __socfpga_periph_init()
83 periph_clk->div_reg = clk_mgr_base_addr + div_reg[0]; __socfpga_periph_init()
H A Dclk.h35 extern void __iomem *clk_mgr_base_addr;

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