Searched refs:cfgcr2 (Results 1 – 4 of 4) sorted by relevance
1566 uint32_t ctrl1, cfgcr1, cfgcr2; in skl_ddi_pll_select() local1588 cfgcr2 = DPLL_CFGCR2_QDIV_RATIO(wrpll_params.qdiv_ratio) | in skl_ddi_pll_select()1607 cfgcr1 = cfgcr2 = 0; in skl_ddi_pll_select()1616 crtc_state->dpll_hw_state.cfgcr2 = cfgcr2; in skl_ddi_pll_select()2565 u32 ctl, cfgcr1, cfgcr2; member2574 .cfgcr2 = DPLL_CFGCR2(SKL_DPLL1),2580 .cfgcr2 = DPLL_CFGCR2(SKL_DPLL2),2586 .cfgcr2 = DPLL_CFGCR2(SKL_DPLL3),2610 I915_WRITE(regs[pll->id].cfgcr2, pll->config.hw_state.cfgcr2); in skl_ddi_pll_enable()2612 POSTING_READ(regs[pll->id].cfgcr2); in skl_ddi_pll_enable()[all …]
384 uint32_t cfgcr1, cfgcr2; member
1121 pipe_config->dpll_hw_state.cfgcr2 = 0; in skl_edp_set_pll_config()
12083 pipe_config->dpll_hw_state.cfgcr2); in intel_dump_pipe_config()12617 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2); in intel_pipe_config_compare()