Searched refs:bootcr (Results 1 - 2 of 2) sorted by relevance

/linux-4.4.14/arch/mips/ar7/
H A Dclock.c173 u32 *bootcr, u32 bus_clock) tnetd7300_get_clock()
184 switch ((*bootcr & (BOOT_PLL_SOURCE_MASK << shift)) >> shift) { tnetd7300_get_clock()
199 if (*bootcr & BOOT_PLL_BYPASS) tnetd7300_get_clock()
219 u32 *bootcr, u32 frequency) tnetd7300_set_clock()
224 switch ((*bootcr & (BOOT_PLL_SOURCE_MASK << shift)) >> shift) { tnetd7300_set_clock()
252 u32 *bootcr = (u32 *)ioremap_nocache(AR7_REGS_DCL, 4); tnetd7300_init_clocks() local
258 &clocks->bus, bootcr, AR7_AFE_CLOCK); tnetd7300_init_clocks()
260 if (*bootcr & BOOT_PLL_ASYNC_MODE) tnetd7300_init_clocks()
262 &clocks->cpu, bootcr, AR7_AFE_CLOCK); tnetd7300_init_clocks()
268 bootcr, dsp_clk.rate); tnetd7300_init_clocks()
271 iounmap(bootcr); tnetd7300_init_clocks()
308 static int tnetd7200_get_clock_base(int clock_id, u32 *bootcr) tnetd7200_get_clock_base() argument
310 if (*bootcr & BOOT_PLL_ASYNC_MODE) tnetd7200_get_clock_base()
320 if (*bootcr & BOOT_PLL_2TO1_MODE) tnetd7200_get_clock_base()
336 u32 *bootcr = (u32 *)ioremap_nocache(AR7_REGS_DCL, 4); tnetd7200_init_clocks() local
344 cpu_base = tnetd7200_get_clock_base(TNETD7200_CLOCK_ID_CPU, bootcr); tnetd7200_init_clocks()
345 dsp_base = tnetd7200_get_clock_base(TNETD7200_CLOCK_ID_DSP, bootcr); tnetd7200_init_clocks()
347 if (*bootcr & BOOT_PLL_ASYNC_MODE) { tnetd7200_init_clocks()
369 if (*bootcr & BOOT_PLL_2TO1_MODE) { tnetd7200_init_clocks()
414 iounmap(bootcr); tnetd7200_init_clocks()
172 tnetd7300_get_clock(u32 shift, struct tnetd7300_clock *clock, u32 *bootcr, u32 bus_clock) tnetd7300_get_clock() argument
218 tnetd7300_set_clock(u32 shift, struct tnetd7300_clock *clock, u32 *bootcr, u32 frequency) tnetd7300_set_clock() argument
H A Dplatform.c653 void __iomem *bootcr; ar7_register_devices() local
714 bootcr = ioremap_nocache(AR7_REGS_DCL, 4); ar7_register_devices()
715 val = readl(bootcr); ar7_register_devices()
716 iounmap(bootcr); ar7_register_devices()

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