Searched refs:afe_write (Results 1 - 2 of 2) sorted by relevance

/linux-4.4.14/drivers/media/i2c/
H A Dadv7842.c485 static inline int afe_write(struct v4l2_subdev *sd, u8 reg, u8 val) afe_write() function
494 return afe_write(sd, reg, (afe_read(sd, reg) & mask) | val); afe_write_and_or()
957 afe_write(sd, reg->reg & 0xff, val); adv7842_s_register()
1318 afe_write(sd, 0xc8, ctrl->val); adv7842_s_ctrl()
1799 afe_write(sd, 0x00, 0x00); /* power up ADC */ select_input()
1800 afe_write(sd, 0xc8, 0x00); /* phase control */ select_input()
1808 afe_write(sd, 0x03, 0xa0); /* ADC0 to AIN10 (CVBS), ADC1 N/C*/ select_input()
1809 afe_write(sd, 0x04, 0x00); /* ADC2 N/C,ADC3 N/C*/ select_input()
1811 afe_write(sd, 0x03, 0xa0); /* ADC0 to AIN10 (CVBS), ADC1 N/C*/ select_input()
1812 afe_write(sd, 0x04, 0xc0); /* ADC2 to AIN12, ADC3 N/C*/ select_input()
1814 afe_write(sd, 0x0c, 0x1f); /* ADI recommend write */ select_input()
1815 afe_write(sd, 0x12, 0x63); /* ADI recommend write */ select_input()
1847 afe_write(sd, 0x00, 0x00); /* power up ADC */ select_input()
1848 afe_write(sd, 0xc8, 0x00); /* phase control */ select_input()
1860 afe_write(sd, 0x0c, 0x1f); /* ADC Range improvement */ select_input()
1861 afe_write(sd, 0x12, 0x63); /* ADC Range improvement */ select_input()
1912 afe_write(sd, 0x00, 0xff); /* power down ADC */ select_input()
1913 afe_write(sd, 0xc8, 0x40); /* phase control */ select_input()
1924 afe_write(sd, 0x12, 0xfb); /* ADC noise shaping filter controls */ select_input()
1925 afe_write(sd, 0x0c, 0x0d); /* CP core gain controls */ select_input()
2800 afe_write(sd, 0xb5, 0x01); /* Setting MCLK to 256Fs */ adv7842_core_init()
2802 afe_write(sd, 0x02, pdata->ain_sel); /* Select analog input muxing mode */ adv7842_core_init()
2878 afe_write(sd, 0x80, 0x92); /* SDP Recommeneded Write */ adv7842_ddr_ram_test()
2879 afe_write(sd, 0x9B, 0x01); /* SDP Recommeneded Write ADV7844ES1 */ adv7842_ddr_ram_test()
2880 afe_write(sd, 0x9C, 0x60); /* SDP Recommeneded Write ADV7844ES1 */ adv7842_ddr_ram_test()
2881 afe_write(sd, 0x9E, 0x02); /* SDP Recommeneded Write ADV7844ES1 */ adv7842_ddr_ram_test()
2882 afe_write(sd, 0xA0, 0x0B); /* SDP Recommeneded Write ADV7844ES1 */ adv7842_ddr_ram_test()
2883 afe_write(sd, 0xC3, 0x02); /* Memory BIST Initialisation */ adv7842_ddr_ram_test()
H A Dadv7604.c487 static inline int afe_write(struct v4l2_subdev *sd, u8 reg, u8 val) afe_write() function
1203 afe_write(sd, 0xc8, ctrl->val); adv76xx_s_ctrl()
1737 afe_write(sd, 0x00, 0x08); /* power up ADC */ select_input()
1738 afe_write(sd, 0x01, 0x06); /* power up Analog Front End */ select_input()
1739 afe_write(sd, 0xc8, 0x00); /* phase control */ select_input()
1746 afe_write(sd, 0x00, 0xff); /* power down ADC */ select_input()
1747 afe_write(sd, 0x01, 0xfe); /* power down Analog Front End */ select_input()
1748 afe_write(sd, 0xc8, 0x40); /* phase control */ select_input()
2517 afe_write(sd, 0xb5, 0x01); /* Setting MCLK to 256Fs */ adv76xx_core_init()
2520 afe_write(sd, 0x02, pdata->ain_sel); /* Select analog input muxing mode */ adv76xx_core_init()

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