Searched refs:VAL (Results 1 - 49 of 49) sorted by relevance

/linux-4.4.14/arch/arm64/kernel/
H A Dhw_breakpoint.c69 #define READ_WB_REG_CASE(OFF, N, REG, VAL) \
71 AARCH64_DBG_READ(N, REG, VAL); \
74 #define WRITE_WB_REG_CASE(OFF, N, REG, VAL) \
76 AARCH64_DBG_WRITE(N, REG, VAL); \
79 #define GEN_READ_WB_REG_CASES(OFF, REG, VAL) \
80 READ_WB_REG_CASE(OFF, 0, REG, VAL); \
81 READ_WB_REG_CASE(OFF, 1, REG, VAL); \
82 READ_WB_REG_CASE(OFF, 2, REG, VAL); \
83 READ_WB_REG_CASE(OFF, 3, REG, VAL); \
84 READ_WB_REG_CASE(OFF, 4, REG, VAL); \
85 READ_WB_REG_CASE(OFF, 5, REG, VAL); \
86 READ_WB_REG_CASE(OFF, 6, REG, VAL); \
87 READ_WB_REG_CASE(OFF, 7, REG, VAL); \
88 READ_WB_REG_CASE(OFF, 8, REG, VAL); \
89 READ_WB_REG_CASE(OFF, 9, REG, VAL); \
90 READ_WB_REG_CASE(OFF, 10, REG, VAL); \
91 READ_WB_REG_CASE(OFF, 11, REG, VAL); \
92 READ_WB_REG_CASE(OFF, 12, REG, VAL); \
93 READ_WB_REG_CASE(OFF, 13, REG, VAL); \
94 READ_WB_REG_CASE(OFF, 14, REG, VAL); \
95 READ_WB_REG_CASE(OFF, 15, REG, VAL)
97 #define GEN_WRITE_WB_REG_CASES(OFF, REG, VAL) \
98 WRITE_WB_REG_CASE(OFF, 0, REG, VAL); \
99 WRITE_WB_REG_CASE(OFF, 1, REG, VAL); \
100 WRITE_WB_REG_CASE(OFF, 2, REG, VAL); \
101 WRITE_WB_REG_CASE(OFF, 3, REG, VAL); \
102 WRITE_WB_REG_CASE(OFF, 4, REG, VAL); \
103 WRITE_WB_REG_CASE(OFF, 5, REG, VAL); \
104 WRITE_WB_REG_CASE(OFF, 6, REG, VAL); \
105 WRITE_WB_REG_CASE(OFF, 7, REG, VAL); \
106 WRITE_WB_REG_CASE(OFF, 8, REG, VAL); \
107 WRITE_WB_REG_CASE(OFF, 9, REG, VAL); \
108 WRITE_WB_REG_CASE(OFF, 10, REG, VAL); \
109 WRITE_WB_REG_CASE(OFF, 11, REG, VAL); \
110 WRITE_WB_REG_CASE(OFF, 12, REG, VAL); \
111 WRITE_WB_REG_CASE(OFF, 13, REG, VAL); \
112 WRITE_WB_REG_CASE(OFF, 14, REG, VAL); \
113 WRITE_WB_REG_CASE(OFF, 15, REG, VAL)
/linux-4.4.14/arch/arm/include/asm/
H A Dhw_breakpoint.h105 #define ARM_DBG_READ(N, M, OP2, VAL) do {\
106 asm volatile("mrc p14, 0, %0, " #N "," #M ", " #OP2 : "=r" (VAL));\
109 #define ARM_DBG_WRITE(N, M, OP2, VAL) do {\
110 asm volatile("mcr p14, 0, %0, " #N "," #M ", " #OP2 : : "r" (VAL));\
/linux-4.4.14/arch/arm/kernel/
H A Dhw_breakpoint.c59 #define READ_WB_REG_CASE(OP2, M, VAL) \
61 ARM_DBG_READ(c0, c ## M, OP2, VAL); \
64 #define WRITE_WB_REG_CASE(OP2, M, VAL) \
66 ARM_DBG_WRITE(c0, c ## M, OP2, VAL); \
69 #define GEN_READ_WB_REG_CASES(OP2, VAL) \
70 READ_WB_REG_CASE(OP2, 0, VAL); \
71 READ_WB_REG_CASE(OP2, 1, VAL); \
72 READ_WB_REG_CASE(OP2, 2, VAL); \
73 READ_WB_REG_CASE(OP2, 3, VAL); \
74 READ_WB_REG_CASE(OP2, 4, VAL); \
75 READ_WB_REG_CASE(OP2, 5, VAL); \
76 READ_WB_REG_CASE(OP2, 6, VAL); \
77 READ_WB_REG_CASE(OP2, 7, VAL); \
78 READ_WB_REG_CASE(OP2, 8, VAL); \
79 READ_WB_REG_CASE(OP2, 9, VAL); \
80 READ_WB_REG_CASE(OP2, 10, VAL); \
81 READ_WB_REG_CASE(OP2, 11, VAL); \
82 READ_WB_REG_CASE(OP2, 12, VAL); \
83 READ_WB_REG_CASE(OP2, 13, VAL); \
84 READ_WB_REG_CASE(OP2, 14, VAL); \
85 READ_WB_REG_CASE(OP2, 15, VAL)
87 #define GEN_WRITE_WB_REG_CASES(OP2, VAL) \
88 WRITE_WB_REG_CASE(OP2, 0, VAL); \
89 WRITE_WB_REG_CASE(OP2, 1, VAL); \
90 WRITE_WB_REG_CASE(OP2, 2, VAL); \
91 WRITE_WB_REG_CASE(OP2, 3, VAL); \
92 WRITE_WB_REG_CASE(OP2, 4, VAL); \
93 WRITE_WB_REG_CASE(OP2, 5, VAL); \
94 WRITE_WB_REG_CASE(OP2, 6, VAL); \
95 WRITE_WB_REG_CASE(OP2, 7, VAL); \
96 WRITE_WB_REG_CASE(OP2, 8, VAL); \
97 WRITE_WB_REG_CASE(OP2, 9, VAL); \
98 WRITE_WB_REG_CASE(OP2, 10, VAL); \
99 WRITE_WB_REG_CASE(OP2, 11, VAL); \
100 WRITE_WB_REG_CASE(OP2, 12, VAL); \
101 WRITE_WB_REG_CASE(OP2, 13, VAL); \
102 WRITE_WB_REG_CASE(OP2, 14, VAL); \
103 WRITE_WB_REG_CASE(OP2, 15, VAL)
/linux-4.4.14/arch/arm64/include/asm/
H A Dhw_breakpoint.h99 #define AARCH64_DBG_READ(N, REG, VAL) do {\
100 asm volatile("mrs %0, dbg" REG #N "_el1" : "=r" (VAL));\
103 #define AARCH64_DBG_WRITE(N, REG, VAL) do {\
104 asm volatile("msr dbg" REG #N "_el1, %0" :: "r" (VAL));\
/linux-4.4.14/drivers/gpio/
H A Dgpio-it87.c43 #define VAL 0x2f macro
105 outb(0x02, VAL); superio_exit()
112 outb(ldn, VAL); superio_select()
118 return inb(VAL); superio_inb()
124 outb(val, VAL); superio_outb()
132 val = inb(VAL) << 8; superio_inw()
134 val |= inb(VAL); superio_inw()
141 outb(val >> 8, VAL); superio_outw()
143 outb(val, VAL); superio_outw()
/linux-4.4.14/drivers/net/ethernet/qlogic/qlcnic/
H A Dqlcnic_hdr.h642 #define QLC_DEV_SET_REF_CNT(VAL, FN) ((VAL) |= (1 << (FN * 4)))
643 #define QLC_DEV_CLR_REF_CNT(VAL, FN) ((VAL) &= ~(1 << (FN * 4)))
644 #define QLC_DEV_SET_RST_RDY(VAL, FN) ((VAL) |= (1 << (FN * 4)))
645 #define QLC_DEV_SET_QSCNT_RDY(VAL, FN) ((VAL) |= (2 << (FN * 4)))
646 #define QLC_DEV_CLR_RST_QSCNT(VAL, FN) ((VAL) &= ~(3 << (FN * 4)))
648 #define QLC_DEV_GET_DRV(VAL, FN) (0xf & ((VAL) >> (FN * 4)))
649 #define QLC_DEV_SET_DRV(VAL, FN) ((VAL) << (FN * 4))
679 #define ISR_LEGACY_INT_TRIGGERED(VAL) (((VAL) & 0x300) == 0x200)
H A Dqlcnic_83xx_hw.h406 #define QLC_83XX_GET_FUNC_PRIVILEGE(VAL, FN) (0x3 & ((VAL) >> (FN * 2)))
407 #define QLC_83XX_SET_FUNC_OPMODE(VAL, FN) ((VAL) << (FN * 2))
H A Dqlcnic.h883 #define QLCNIC_IS_LB_CONFIGURED(VAL) \
884 (VAL == (QLCNIC_LINKEVENT | QLCNIC_LB_RESPONSE))
/linux-4.4.14/drivers/rtc/
H A Drtc-at32ap700x.c75 now = rtc_readl(rtc, VAL); at32_rtc_readtime()
89 rtc_writel(rtc, VAL, now); at32_rtc_settime()
114 rtc_unix_time = rtc_readl(rtc, VAL); at32_rtc_setalarm()
145 if (rtc_readl(rtc, VAL) > rtc->alarm_time) { at32_rtc_alarm_irq_enable()
179 rtc_writel(rtc, VAL, rtc->alarm_time); at32_rtc_interrupt()
233 * Do not reset VAL register, as it can hold an old time at32_rtc_probe()
/linux-4.4.14/include/linux/
H A Ddma-mapping.h309 #define dma_unmap_addr_set(PTR, ADDR_NAME, VAL) (((PTR)->ADDR_NAME) = (VAL))
311 #define dma_unmap_len_set(PTR, LEN_NAME, VAL) (((PTR)->LEN_NAME) = (VAL))
316 #define dma_unmap_addr_set(PTR, ADDR_NAME, VAL) do { } while (0)
318 #define dma_unmap_len_set(PTR, LEN_NAME, VAL) do { } while (0)
/linux-4.4.14/drivers/watchdog/
H A Dit8712f_wdt.c62 #define VAL 0x2f /* The value to read/write */ macro
100 return inb(VAL); superio_inb()
106 outb(val, VAL); superio_outb()
113 val = inb(VAL) << 8; superio_inw()
115 val |= inb(VAL); superio_inw()
122 outb(ldn, VAL); superio_select()
143 outb(0x02, VAL); superio_exit()
H A Dit87_wdt.c65 #define VAL 0x2f macro
192 outb(0x02, VAL); superio_exit()
199 outb(ldn, VAL); superio_select()
205 return inb(VAL); superio_inb()
211 outb(val, VAL); superio_outb()
218 val = inb(VAL) << 8; superio_inw()
220 val |= inb(VAL); superio_inw()
227 outb(val >> 8, VAL); superio_outw()
229 outb(val, VAL); superio_outw()
/linux-4.4.14/drivers/scsi/
H A Dsun3x_esp.c44 #define dma_write32(VAL, REG) \
45 writel((VAL), esp->dma_regs + (REG))
49 #define dma_write32(VAL, REG) \
50 do { *(volatile u32 *)(esp->dma_regs + (REG)) = (VAL); } while (0)
H A Daha152x.h288 #define SETPORT(PORT, VAL) outb( (VAL), (PORT) )
H A Dmac_esp.c49 #define esp_write8(VAL, REG) mac_esp_write8(esp, VAL, REG)
H A Dsun_esp.c32 #define dma_write32(VAL, REG) \
33 sbus_writel((VAL), esp->dma_regs + (REG))
H A Desp_scsi.c116 #define esp_write8(VAL,REG) esp->ops->esp_write8(esp, VAL, REG)
/linux-4.4.14/drivers/net/ethernet/qlogic/netxen/
H A Dnetxen_nic_hdr.h966 #define NETXEN_DIMM_MEMTYPE(VAL) ((VAL >> 3) & 0xf)
967 #define NETXEN_DIMM_NUMROWS(VAL) ((VAL >> 7) & 0xf)
968 #define NETXEN_DIMM_NUMCOLS(VAL) ((VAL >> 11) & 0xf)
969 #define NETXEN_DIMM_NUMRANKS(VAL) ((VAL >> 15) & 0x3)
970 #define NETXEN_DIMM_DATAWIDTH(VAL) ((VAL >> 18) & 0x3)
971 #define NETXEN_DIMM_NUMBANKS(VAL) ((VAL >> 21) & 0xf)
972 #define NETXEN_DIMM_TYPE(VAL) ((VAL >> 25) & 0x3f)
1007 #define ISR_LEGACY_INT_TRIGGERED(VAL) (((VAL) & 0x300) == 0x200)
/linux-4.4.14/sound/soc/codecs/
H A Dtlv320aic31xx.h51 /* PLL P and R-VAL register */
53 /* PLL J-VAL register */
55 /* PLL D-VAL MSB register */
57 /* PLL D-VAL LSB register */
H A Duda1380.c120 pr_debug("uda1380: READ BACK VAL %x\n", uda1380_write()
/linux-4.4.14/drivers/net/ethernet/freescale/fs_enet/
H A Dmii-fec.c47 #define mk_mii_write(REG, VAL) (0x50020000 | ((REG & 0x1f) << 18) | (VAL & 0xffff))
H A Dmac-fcc.c74 #define mk_mii_write(REG, VAL) (0x50020000 | ((REG & 0x1f) << 18) | (VAL & 0xffff))
/linux-4.4.14/arch/metag/include/asm/
H A Dmetag_isa.h74 #define CRLINPHY0_FIRST_BIT 0x00000004 /* Set if VAL=0 due to first level */
/linux-4.4.14/drivers/hwmon/
H A Dsmsc47b397.c55 #define VAL 0x2f /* The value to read/write */ macro
60 outb(val, VAL); superio_outb()
66 return inb(VAL); superio_inb()
H A Dsmsc47m1.c57 #define VAL 0x2f /* The value to read/write */ macro
63 outb(val, VAL); superio_outb()
70 return inb(VAL); superio_inb()
H A Dit87.c85 #define VAL 0x2f /* The value to read/write */ macro
97 return inb(VAL); superio_inb()
103 outb(val, VAL); superio_outb()
110 val = inb(VAL) << 8; superio_inw()
112 val |= inb(VAL); superio_inw()
119 outb(ldn, VAL); superio_select()
140 outb(0x02, VAL); superio_exit()
/linux-4.4.14/drivers/net/ethernet/amd/
H A Damd8111e.h186 VAL3 = (1 << 31), /* VAL bit for byte 3 */
187 VAL2 = (1 << 23), /* VAL bit for byte 2 */
188 VAL1 = (1 << 15), /* VAL bit for byte 1 */
189 VAL0 = (1 << 7), /* VAL bit for byte 0 */
/linux-4.4.14/arch/sparc/include/asm/
H A Dtsb.h112 #define TSB_STORE(ADDR, VAL) \
113 661: stxa VAL, [ADDR] ASI_N; \
116 stxa VAL, [ADDR] ASI_PHYS_USE_EC; \
/linux-4.4.14/drivers/scsi/qla2xxx/
H A Dqla_nx.h703 #define ISR_IS_LEGACY_INTR_IDLE(VAL) (((VAL) & 0x300) == 0)
704 #define ISR_IS_LEGACY_INTR_TRIGGERED(VAL) (((VAL) & 0x300) == 0x200)
/linux-4.4.14/drivers/scsi/qla4xxx/
H A Dql4_nx.h764 #define ISR_IS_LEGACY_INTR_IDLE(VAL) (((VAL) & 0x300) == 0)
765 #define ISR_IS_LEGACY_INTR_TRIGGERED(VAL) (((VAL) & 0x300) == 0x200)
/linux-4.4.14/drivers/staging/comedi/drivers/
H A Ds626.h366 #define S626_I2C_B2(ATTR, VAL) (((ATTR) << 6) | ((VAL) << 24))
367 #define S626_I2C_B1(ATTR, VAL) (((ATTR) << 4) | ((VAL) << 16))
368 #define S626_I2C_B0(ATTR, VAL) (((ATTR) << 2) | ((VAL) << 8))
/linux-4.4.14/drivers/uwb/i1480/dfu/
H A Dphy.c160 * (which gives us 160 byte triads of MSB, LSB and VAL for the data).
/linux-4.4.14/drivers/video/fbdev/omap2/displays-new/
H A Dpanel-nec-nl8048hl11.c111 /* nec_8048_spi_send(spi, REG, VAL) */ init_nec_8048_wvga_lcd()
/linux-4.4.14/drivers/media/dvb-frontends/
H A Ddrxk_hard.h265 bool m_invert_val; /* If TRUE, invert VAL signals */
H A Ddrxk_hard.c735 state->m_invert_val = false; /* If TRUE; invert VAL signals */ init_state()
/linux-4.4.14/arch/tile/kernel/
H A Dtraps.c147 /* There must be an "addli zero, zero, VAL" in X0. */ special_ill()
H A Dpci_gx.c51 pr_info("CFG WR %d-byte VAL %#x to bus %d dev %d func %d addr %u\n", \
54 pr_info("CFG RD %d-byte VAL %#x from bus %d dev %d func %d addr %u\n", \
/linux-4.4.14/drivers/net/ethernet/
H A Djme.h1224 reg_dbg(jme, "VAL AFTER WRITE", readl(jme->regs + reg), reg); jwrite32()
1235 reg_dbg(jme, "VAL AFTER WRITE", readl(jme->regs + reg), reg); jwrite32f()
/linux-4.4.14/drivers/power/
H A Daxp288_fuel_gauge.c456 * [12-bit ADC VAL] = R_NTC(Ω) * current / 800 temp_to_adc()
478 * R_NTC(Ω) = [12-bit ADC VAL] * 800 / current adc_to_temp()
/linux-4.4.14/sound/core/oss/
H A Dpcm_oss.c262 * values < VAL. Reduce configuration space accordingly.
323 * values >= VAL + 1. Reduce configuration space accordingly.
395 * nearest to VAL. Reduce configuration space accordingly.
529 * values != VAL. Reduce configuration space accordingly.
530 * Return VAL or -EINVAL if the configuration space is empty
/linux-4.4.14/tools/testing/ktest/
H A Dktest.pl829 while ($val =~ s/\(([^\(]*?)\)/\&\&\&\&VAL\&\&\&\&/) {
833 $val =~ s/\&\&\&\&VAL\&\&\&\&/ 1 /;
835 $val =~ s/\&\&\&\&VAL\&\&\&\&/ 0 /;
/linux-4.4.14/drivers/pinctrl/nomadik/
H A Dpinctrl-nomadik.c172 /* Shortcuts. Use these instead of separate DIR, PULL, and VAL. */
1007 seq_printf(s, " VAL %d", val); nmk_gpio_dbg_show_one()
/linux-4.4.14/drivers/block/
H A Dskd_main.c356 #define SKD_WRITEL(DEV, VAL, OFF) skd_reg_write32(DEV, VAL, OFF)
358 #define SKD_WRITEQ(DEV, VAL, OFF) skd_reg_write64(DEV, VAL, OFF)
/linux-4.4.14/drivers/net/hippi/
H A Drrunner.c538 * other method I've seen. -VAL rr_init()
/linux-4.4.14/tools/perf/util/
H A Dprobe-finder.c1305 strbuf_addf(&buf, "[VAL]\t"); collect_variables_cb()
/linux-4.4.14/drivers/media/dvb-frontends/drx39xyj/
H A Ddrx_driver.h1336 bool invert_val; /**< If true, invert VAL signals */
H A Ddrxj.c841 false, /* If true, invert VAL signals */
/linux-4.4.14/arch/ia64/kernel/
H A Dptrace.c392 * is the user-level address to read the word from, VAL a pointer to
/linux-4.4.14/drivers/staging/rdma/hfi1/
H A Dchip.c2956 /* set tx fifo reset: LCB_CFG_TX_FIFOS_RESET.VAL = 1 */ lcb_shutdown()
5291 /* LCB_CFG_LOOPBACK.VAL = 2 */ do_quick_linkup()
5292 /* LCB_CFG_LANE_WIDTH.VAL = 0 */ do_quick_linkup()
5299 /* LCB_CFG_TX_FIFOS_RESET.VAL = 0 */ do_quick_linkup()

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