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Searched refs:PINMUX_CFG_REG_VAR (Results 1 – 9 of 9) sorted by relevance

/linux-4.4.14/drivers/pinctrl/sh-pfc/
Dpfc-r8a7791.c5413 { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32,
5472 { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060024, 32,
5508 { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32,
5544 { PINMUX_CFG_REG_VAR("IPSR3", 0xE606002C, 32,
5582 { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32,
5624 { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060034, 32,
5662 { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32,
5702 { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32,
5743 { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32,
5786 { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32,
[all …]
Dpfc-sh7734.c1833 { PINMUX_CFG_REG_VAR("IPSR0", 0xFFFC001C, 32,
1870 { PINMUX_CFG_REG_VAR("IPSR1", 0xFFFC0020, 32,
1905 { PINMUX_CFG_REG_VAR("IPSR2", 0xFFFC0024, 32,
1941 { PINMUX_CFG_REG_VAR("IPSR3", 0xFFFC0028, 32,
1978 { PINMUX_CFG_REG_VAR("IPSR4", 0xFFFC002C, 32,
2013 { PINMUX_CFG_REG_VAR("IPSR5", 0xFFFC0030, 32,
2053 { PINMUX_CFG_REG_VAR("IPSR6", 0xFFFC0034, 32,
2097 { PINMUX_CFG_REG_VAR("IPSR7", 0xFFFC0038, 32,
2133 { PINMUX_CFG_REG_VAR("IPSR8", 0xFFFC003C, 32,
2169 { PINMUX_CFG_REG_VAR("IPSR9", 0xFFFC0040, 32,
[all …]
Dpfc-emev2.c1594 { PINMUX_CFG_REG_VAR("CHG_PINSEL_LCD3", 0xe0140284, 32,
1612 { PINMUX_CFG_REG_VAR("CHG_PINSEL_UART", 0xe0140288, 32,
1624 { PINMUX_CFG_REG_VAR("CHG_PINSEL_IIC", 0xe014028c, 32,
1636 { PINMUX_CFG_REG_VAR("CHG_PINSEL_AB", 0xe0140294, 32,
1661 { PINMUX_CFG_REG_VAR("CHG_PINSEL_USI", 0xe0140298, 32,
1680 { PINMUX_CFG_REG_VAR("CHG_PINSEL_HSI", 0xe01402a8, 32,
Dpfc-r8a7790.c4952 { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32,
4988 { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060024, 32,
5025 { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32,
5054 { PINMUX_CFG_REG_VAR("IPSR3", 0xE606002C, 32,
5087 { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32,
5120 { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060034, 32,
5157 { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32,
5193 { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32,
5228 { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32,
5269 { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32,
[all …]
Dpfc-r8a7778.c2285 { PINMUX_CFG_REG_VAR("IPSR0", 0xfffc0020, 32,
2340 { PINMUX_CFG_REG_VAR("IPSR1", 0xfffc0024, 32,
2383 { PINMUX_CFG_REG_VAR("IPSR2", 0xfffc0028, 32,
2435 { PINMUX_CFG_REG_VAR("IPSR3", 0xfffc002c, 32,
2477 { PINMUX_CFG_REG_VAR("IPSR4", 0xfffc0030, 32,
2519 { PINMUX_CFG_REG_VAR("IPSR5", 0xfffc0034, 32,
2563 { PINMUX_CFG_REG_VAR("IPSR6", 0xfffc0038, 32,
2614 { PINMUX_CFG_REG_VAR("IPSR7", 0xfffc003c, 32,
2653 { PINMUX_CFG_REG_VAR("IPSR8", 0xfffc0040, 32,
2693 { PINMUX_CFG_REG_VAR("IPSR9", 0xfffc0044, 32,
[all …]
Dpfc-r8a7779.c3239 { PINMUX_CFG_REG_VAR("IPSR0", 0xfffc0020, 32,
3277 { PINMUX_CFG_REG_VAR("IPSR1", 0xfffc0024, 32,
3315 { PINMUX_CFG_REG_VAR("IPSR2", 0xfffc0028, 32,
3361 { PINMUX_CFG_REG_VAR("IPSR3", 0xfffc002c, 32,
3412 { PINMUX_CFG_REG_VAR("IPSR4", 0xfffc0030, 32,
3460 { PINMUX_CFG_REG_VAR("IPSR5", 0xfffc0034, 32,
3506 { PINMUX_CFG_REG_VAR("IPSR6", 0xfffc0038, 32,
3543 { PINMUX_CFG_REG_VAR("IPSR7", 0xfffc003c, 32,
3579 { PINMUX_CFG_REG_VAR("IPSR8", 0xfffc0040, 32,
3622 { PINMUX_CFG_REG_VAR("IPSR9", 0xfffc0044, 32,
[all …]
Dpfc-r8a7794.c3692 { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32,
3746 { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060024, 32,
3786 { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32,
3821 { PINMUX_CFG_REG_VAR("IPSR3", 0xE606002C, 32,
3861 { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32,
3896 { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060034, 32,
3931 { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32,
3976 { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32,
4013 { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32,
4048 { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32,
[all …]
Dsh_pfc.h107 #define PINMUX_CFG_REG_VAR(name, r, r_width, var_fw0, var_fwn...) \ macro
334 PINMUX_CFG_REG_VAR("PORT" nr "CR", reg, 8, 2, 2, 1, 3) {\
Dpfc-r8a7795.c2711 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
2738 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
2765 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32,