Searched refs:MDMA_D2_IRQ_STATUS (Results 1 - 6 of 6) sorted by relevance

/linux-4.4.14/arch/blackfin/mach-bf561/include/mach/
H A DcdefBF561.h862 #define bfin_read_MDMA_D2_IRQ_STATUS() bfin_read16(MDMA_D2_IRQ_STATUS)
863 #define bfin_write_MDMA_D2_IRQ_STATUS(val) bfin_write16(MDMA_D2_IRQ_STATUS,val)
H A DdefBF561.h719 #define MDMA_D2_IRQ_STATUS 0xFFC00F28 /*MemDMA2 Stream 0 Dest Interrupt/Status Register */ macro
/linux-4.4.14/arch/blackfin/mach-bf538/include/mach/
H A DcdefBF538.h1132 #define bfin_read_MDMA_D2_IRQ_STATUS() bfin_read16(MDMA_D2_IRQ_STATUS)
1133 #define bfin_write_MDMA_D2_IRQ_STATUS(val) bfin_write16(MDMA_D2_IRQ_STATUS, val)
H A DdefBF538.h615 #define MDMA_D2_IRQ_STATUS 0xFFC01F28 /* MemDMA1 Stream 0 Destination Interrupt/Status Register */ macro
/linux-4.4.14/arch/blackfin/mach-bf548/include/mach/
H A DcdefBF54x_base.h1529 #define bfin_read_MDMA_D2_IRQ_STATUS() bfin_read16(MDMA_D2_IRQ_STATUS)
1530 #define bfin_write_MDMA_D2_IRQ_STATUS(val) bfin_write16(MDMA_D2_IRQ_STATUS, val)
H A DdefBF54x_base.h898 #define MDMA_D2_IRQ_STATUS 0xffc01f28 /* Memory DMA Stream 2 Destination Interrupt/Status Register */ macro

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