| /linux-4.4.14/net/l3mdev/ |
| D | Kconfig | 2 # Configuration for L3 master device support
6 bool "L3 Master device support"
10 drivers to support L3 master devices like VRF.
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| /linux-4.4.14/Documentation/networking/ |
| D | ipvlan.txt | 9 exception of using L3 for mux-ing /demux-ing among slaves. This property makes
25 ip link add link <master-dev> <slave-dev> type ipvlan mode { l2 | L3 }
31 IPvlan has two modes of operation - L2 and L3. For a given master device,
34 that in L3 mode the slaves wont receive any multicast / broadcast traffic.
35 L3 mode is more restrictive since routing is controlled from the other (mostly)
44 4.2 L3 mode:
45 In this mode TX processing upto L3 happens on the stack instance attached
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| D | switchdev.txt | 79 level constructs such as bridges, bonds, VLANs, tunnels, and L3 routers. Using
143 router port, used to offload L3 forwarding. Two or more ports can be bonded
145 L2 networks. VLANs can be applied to sub-divide L2 networks. L2-over-L3
310 L3 Routing Offload
313 Offloading L3 routing requires that device be programmed with FIB entries from
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| D | vrf.txt | 20 L2 separation and then VRF devices provide L3 separation.
70 3. Enslave L3 interfaces to a VRF device.
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| /linux-4.4.14/Documentation/devicetree/bindings/edac/ |
| D | apm-xgene-edac.txt | 8 L3 - L3 cache controller
20 - interrupts : Interrupt-specifier for MCU, PMD, L3, or SoC error
35 Required properties for L3 subnode:
38 - reg : First resource shall be the L3 EDAC resource.
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| /linux-4.4.14/Documentation/devicetree/bindings/sound/ |
| D | omap-mcpdm.txt | 7 <L3 interconnect address, size>;
17 <0x49032000 0x7f>; /* L3 Interconnect */
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| D | omap-dmic.txt | 7 <L3 interconnect address, size>;
17 <0x4902e000 0x7f>; /* L3 Interconnect */
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| D | omap-mcbsp.txt | 10 <L3 interconnect address, size>;
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| /linux-4.4.14/Documentation/devicetree/bindings/arm/omap/ |
| D | l3-noc.txt | 1 * TI - L3 Network On Chip (NoC)
12 - reg: Contains L3 register address range for each noc domain.
|
| /linux-4.4.14/Documentation/devicetree/bindings/arm/uniphier/ |
| D | cache-uniphier.txt | 17 be 2 for L2 cache, 3 for L3 cache, etc.
23 The L2 cache must exist to use the L3 cache; the cache hierarchy must be
38 Example 2 (system with L2 and L3):
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| /linux-4.4.14/arch/m68k/lib/ |
| D | divsi3.S | 115 jpl L3
118 L3: movel sp@+, d2 label
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| D | udivsi3.S | 95 jcc L3 /* then try next algorithm */
107 L3: movel d1, d2 /* use d2 as divisor backup */ label
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| /linux-4.4.14/Documentation/zh_CN/arm64/ |
| D | memory.txt | 88 | | | | +-> [20:12] L3 索引
103 | | | +----------> [28:16] L3 索引
|
| /linux-4.4.14/arch/alpha/kernel/ |
| D | setup.c | 1354 int L1I, L1D, L2, L3; in determine_cpu_caches() local
1365 L3 = -1; in determine_cpu_caches()
1386 L3 = -1; in determine_cpu_caches()
1417 L3 = external_cache_probe(1024*1024, width); in determine_cpu_caches()
1431 L3 = -1; in determine_cpu_caches()
1454 L3 = -1; in determine_cpu_caches()
1461 L3 = -1; in determine_cpu_caches()
1466 L1I = L1D = L2 = L3 = 0; in determine_cpu_caches()
1473 alpha_l3_cacheshape = L3; in determine_cpu_caches()
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| /linux-4.4.14/drivers/cpufreq/ |
| D | s5pv210-cpufreq.c | 111 L0, L1, L2, L3, L4, enumerator
129 {0, L3, 200*1000},
158 [L3] = {
373 if (index >= L3) in s5pv210_target()
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| D | exynos5440-cpufreq.c | 93 L0, L1, L2, L3, L4, enumerator
|
| /linux-4.4.14/arch/metag/tbx/ |
| D | tbidspram.S | 111 $L3:
118 BR $L3
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| /linux-4.4.14/arch/metag/lib/ |
| D | div64.S | 13 BNE $L3
18 $L3:
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| /linux-4.4.14/arch/blackfin/kernel/cplb-mpu/ |
| D | Makefile | 8 -ffixed-L0 -ffixed-L1 -ffixed-L2 -ffixed-L3 \
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| /linux-4.4.14/arch/blackfin/kernel/cplb-nompu/ |
| D | Makefile | 8 -ffixed-L0 -ffixed-L1 -ffixed-L2 -ffixed-L3 \
|
| /linux-4.4.14/Documentation/arm64/ |
| D | memory.txt | 68 | | | | +-> [20:12] L3 index
83 | | | +----------> [28:16] L3 index
|
| /linux-4.4.14/net/switchdev/ |
| D | Kconfig | 11 meaning of the word "switch". This include devices supporting L2/L3 but
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| /linux-4.4.14/arch/x86/kernel/cpu/ |
| D | perf_event_intel_ds.c | 56 P(OP, LOAD) | P(LVL, MISS) | P(LVL, L3) | P(SNOOP, NA),/* 0x00:ukn L3 */
60 OP_LH | P(LVL, L3) | P(SNOOP, NONE), /* 0x04: L3 hit */
61 OP_LH | P(LVL, L3) | P(SNOOP, MISS), /* 0x05: L3 hit, snoop miss */
62 OP_LH | P(LVL, L3) | P(SNOOP, HIT), /* 0x06: L3 hit, snoop hit */
63 OP_LH | P(LVL, L3) | P(SNOOP, HITM), /* 0x07: L3 hit, snoop hitm */
77 pebs_data_source[0x05] = OP_LH | P(LVL, L3) | P(SNOOP, HIT); in intel_pmu_pebs_data_source_nhm()
78 pebs_data_source[0x06] = OP_LH | P(LVL, L3) | P(SNOOP, HITM); in intel_pmu_pebs_data_source_nhm()
79 pebs_data_source[0x07] = OP_LH | P(LVL, L3) | P(SNOOP, HITM); in intel_pmu_pebs_data_source_nhm()
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| /linux-4.4.14/arch/xtensa/lib/ |
| D | memset.S | 91 bbci.l a4, 2, .L3
95 .L3: label
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| D | usercopy.S | 187 bbci.l a4, 2, .L3
193 .L3: label
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| D | memcopy.S | 177 bbsi.l a4, 2, .L3
181 .L3: label
|
| /linux-4.4.14/arch/hexagon/lib/ |
| D | memset.S | 177 if (p0.new) jump:nt .L3
189 .L3: label
|
| /linux-4.4.14/Documentation/devicetree/bindings/ |
| D | resource-names.txt | 28 <1 0 0x49000000 0x00001000>; /* L3 path */
|
| /linux-4.4.14/Documentation/locking/ |
| D | rt-mutex-design.txt | 129 Mutexes: L1, L2, L3, L4
135 C owns L3
136 D blocked on L3
142 E->L4->D->L3->C->L2->B->L1->A
156 E->L4->D->L3->C->L2-+
175 E->L4->D->L3->C-+
239 L1, L2, and L3, and four separate functions func1, func2, func3 and func4.
240 The following shows a locking order of L1->L2->L3, but may not actually
266 mutex_lock(L3);
270 mutex_unlock(L3);
[all …]
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| /linux-4.4.14/arch/arm/mach-omap2/ |
| D | sram242x.S | 100 mov r4, #0x800 @ delay DLL relock, min 0x400 L3 clocks
194 mov r1, #0x2000 @ wait DLL relock, min 0x400 L3 clocks
310 mov r4, #0x800 @ relock time (min 0x400 L3 clocks)
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| D | sram243x.S | 100 mov r4, #0x800 @ delay DLL relock, min 0x400 L3 clocks
194 mov r1, #0x2000 @ wait DLL relock, min 0x400 L3 clocks
310 mov r4, #0x800 @ relock time (min 0x400 L3 clocks)
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| /linux-4.4.14/arch/blackfin/mach-bf561/ |
| D | secondary.S | 50 L3 = r6; define
|
| /linux-4.4.14/arch/arm/boot/dts/ |
| D | omap4.dtsi | 578 <0x49032000 0x7f>; /* L3 Interconnect */
591 <0x4902e000 0x7f>; /* L3 Interconnect */
603 <0x49022000 0xff>; /* L3 Interconnect */
618 <0x49024000 0xff>; /* L3 Interconnect */
633 <0x49026000 0xff>; /* L3 Interconnect */
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| D | omap5.dtsi | 638 <0x49032000 0x7f>; /* L3 Interconnect */
651 <0x4902e000 0x7f>; /* L3 Interconnect */
663 <0x49022000 0xff>; /* L3 Interconnect */
678 <0x49024000 0xff>; /* L3 Interconnect */
693 <0x49026000 0xff>; /* L3 Interconnect */
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| D | omap3-n900.dts | 16 * Default secure signed bootloader (Nokia X-Loader) does not enable L3 firewall
21 * There is "unofficial" version of bootloader which enables AES in L3 firewall
23 * There is also no runtime detection code if AES is disabled in L3 firewall...
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| /linux-4.4.14/arch/blackfin/mach-common/ |
| D | head.S | 59 L3 = r6; define
|
| /linux-4.4.14/Documentation/ABI/testing/ |
| D | sysfs-devices-system-cpu | 166 Description: Disable L3 cache indices
172 disabled index for that node. There is one L3 structure per
177 All AMD processors with L3 caches provide this functionality.
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| /linux-4.4.14/Documentation/arm/SA1100/ |
| D | Assabet | 256 L3: Fully tested, pass.
|
| /linux-4.4.14/drivers/net/ |
| D | Kconfig | 155 and packets will be delivered based on the dest L3 (IPv6/IPv4 addr)
|
| /linux-4.4.14/Documentation/isdn/ |
| D | README | 512 isdnctrl l3_prot <InterfaceName> <L3-ProtocolName>
|
| /linux-4.4.14/Documentation/ |
| D | edac.txt | 40 Some architectures have ECC detectors for L1, L2 and L3 caches,
|