Searched refs:ICLR (Results 1 - 10 of 10) sorted by relevance

/linux-4.4.14/drivers/irqchip/
H A Dirq-sa11x0.c26 #define ICLR 0x08 /* IC Level Reg. */ macro
97 st->iclr = readl_relaxed(iobase + ICLR); sa1100irq_suspend()
114 writel_relaxed(st->iclr, iobase + ICLR); sa1100irq_resume()
161 writel_relaxed(0, iobase + ICLR); sa11x0_init_irq_nodt()
/linux-4.4.14/arch/sparc/include/asm/
H A Dfhc.h72 #define FHC_FFREGS_ICLR 0x10UL /* FHC Fanfail ICLR */
74 #define FHC_SREGS_ICLR 0x10UL /* FHC System ICLR */
76 #define FHC_UREGS_ICLR 0x10UL /* FHC Uart ICLR */
78 #define FHC_TREGS_ICLR 0x10UL /* FHC TOD ICLR */
H A Dirq_64.h17 /* IMAP/ICLR register defines */
/linux-4.4.14/arch/arm/mach-pxa/
H A Dirq.c33 #define ICLR (0x008) macro
163 __raw_writel(0, base + ICLR); /* all IRQs are IRQ, not FIQ */ pxa_init_irq_common()
211 __raw_writel(0, base + ICLR); pxa_irq_resume()
/linux-4.4.14/arch/arm/mach-sa1100/
H A Dpm.c91 ICLR = 0; sa11x0_pm_enter()
/linux-4.4.14/arch/sparc/kernel/
H A Dentry.S347 stha %o1, [%o0] ASI_M_MXCC /* Clear PIL 14 in MXCC's ICLR */
374 stha %o1, [%o0] ASI_M_MXCC /* Clear PIL 15 in MXCC's ICLR */
H A Dirq_64.c424 * ICLR register to reset the state machine.
428 * multiple INOs (and thus ICLR registers). Since we use a different
H A Dprom_irqtrans.c675 * the right ICLR register based upon the lower SBUS irq level sbus_of_build_irq()
H A Dsbus.c224 * the right ICLR register based upon the lower SBUS irq level sbus_build_irq()
/linux-4.4.14/arch/arm/mach-sa1100/include/mach/
H A DSA-1100.h1195 * ICLR Interrupt Controller (IC) Level Register (read/write).
1211 #define ICLR __REG(0x90050008) /* IC Level Reg. */ macro

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