/linux-4.4.14/arch/blackfin/mach-bf538/include/mach/ |
H A D | defBF539.h | 79 #define MXVR_DMA3_CONFIG 0xFFC027D4 /* MXVR Sync Data DMA3 Config Register */ 80 #define MXVR_DMA3_START_ADDR 0xFFC027D8 /* MXVR Sync Data DMA3 Start Address Register */ 81 #define MXVR_DMA3_COUNT 0xFFC027DC /* MXVR Sync Data DMA3 Loop Count Register */ 82 #define MXVR_DMA3_CURR_ADDR 0xFFC027E0 /* MXVR Sync Data DMA3 Current Address Register */ 83 #define MXVR_DMA3_CURR_COUNT 0xFFC027E4 /* MXVR Sync Data DMA3 Current Loop Count Register */
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/linux-4.4.14/arch/sh/drivers/pci/ |
H A D | pci-sh4.h | 61 #define SH4_PCICLR_MDMA3 0x08000000 /* DMA3 Transfer Error */ 103 #define SH4_PCIDPA3 0x1B0 /* DMA3 Transfer Addr. */ 104 #define SH4_PCIDLA3 0x1B4 /* DMA3 Local Addr. */ 105 #define SH4_PCIDTC3 0x1B8 /* DMA3 Transfer Cnt. */ 106 #define SH4_PCIDCR3 0x1BC /* DMA3 Control Register */
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/linux-4.4.14/arch/blackfin/mach-bf548/include/mach/ |
H A D | defBF549.h | 86 /* MXVR DMA3 Registers */ 88 #define MXVR_DMA3_CONFIG 0xffc027d4 /* MXVR Sync Data DMA3 Config Register */ 89 #define MXVR_DMA3_START_ADDR 0xffc027d8 /* MXVR Sync Data DMA3 Start Address */ 90 #define MXVR_DMA3_COUNT 0xffc027dc /* MXVR Sync Data DMA3 Loop Count Register */ 91 #define MXVR_DMA3_CURR_ADDR 0xffc027e0 /* MXVR Sync Data DMA3 Current Address */ 92 #define MXVR_DMA3_CURR_COUNT 0xffc027e4 /* MXVR Sync Data DMA3 Current Loop Count */
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H A D | cdefBF549.h | 138 /* MXVR DMA3 Registers */
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H A D | irq.h | 26 #define IRQ_SPORT1_TX BFIN_IRQ(12) /* SPORT1 TX Interrupt (DMA3) */
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H A D | defBF542.h | 726 #define DMA3_INT 0x8 /* DMA3 pending interrupt */
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H A D | defBF547.h | 1003 #define DMA3_INT 0x8 /* DMA3 pending interrupt */
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H A D | defBF54x_base.h | 1528 #define DMA3 0x1000 /* DMA Channel 3 */ macro
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/linux-4.4.14/arch/blackfin/mach-bf533/include/mach/ |
H A D | irq.h | 25 #define IRQ_SPORT1_RX BFIN_IRQ(11) /* DMA3 Interrupt (SPORT1 RX) */
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/linux-4.4.14/drivers/media/pci/ttpci/ |
H A D | budget-core.c | 68 saa7146_write(budget->dev, MC1, MASK_20); // DMA3 off stop_ts_capture() 82 saa7146_write(dev, MC1, MASK_20); // DMA3 off start_ts_capture() 93 * tuner -> SAA7146 port A -> SAA7146 BRS -> SAA7146 DMA3 -> memory start_ts_capture() 96 * DMA3 is configured to strip the trailing 16 FEC bytes: start_ts_capture() 159 saa7146_write(dev, MC1, (MASK_04 | MASK_20)); /* DMA3 on */ start_ts_capture()
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H A D | av7110.c | 1211 saa7146_write(budget->dev, MC1, MASK_20); /* DMA3 off */ stop_ts_capture() 1230 saa7146_write(budget->dev, MC1, (MASK_04 | MASK_20)); /* DMA3 on */ start_ts_capture() 2785 saa7146_write(saa, MC1, MASK_20); /* DMA3 off */ av7110_detach()
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/linux-4.4.14/arch/powerpc/include/asm/ |
H A D | tsi108_irq.h | 67 #define IRQ_TSI108_DMA3 TSI108_IRQ(11) /* DMA3 */
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/linux-4.4.14/arch/mips/txx9/rbtx4938/ |
H A D | irq.c | 36 * TXX9_IRQ_BASE+13 TX4938 DMA3
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/linux-4.4.14/arch/blackfin/mach-bf537/include/mach/ |
H A D | irq.h | 19 #define IRQ_SPORT0_RX BFIN_IRQ(5) /* DMA3 Interrupt (SPORT0 RX) */
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/linux-4.4.14/drivers/irqchip/ |
H A D | irq-s3c24xx.c | 657 { .type = S3C_IRQTYPE_EDGE, }, /* DMA3 */ 726 { .type = S3C_IRQTYPE_EDGE, }, /* DMA3 */ 864 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA3 */ 931 { .type = S3C_IRQTYPE_EDGE, }, /* DMA3 */ 1006 { .type = S3C_IRQTYPE_EDGE, }, /* DMA3 */ 1116 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA3 */
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/linux-4.4.14/sound/isa/ |
H A D | cmi8328.c | 91 * bits 5-6: SB DMA: 00=disabled (when SB disabled), 01=DMA0, 10=DMA1, 11=DMA3 108 * bits 3-4: CD-ROM DMA: 00=disabled, 01=DMA0, 10=DMA1, 11=DMA3
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/linux-4.4.14/drivers/net/wan/ |
H A D | hostess_sv11.c | 331 MODULE_PARM_DESC(dma, "Set this to 1 to use DMA1/DMA3 for TX/RX");
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/linux-4.4.14/drivers/net/wireless/ath/wcn36xx/ |
H A D | dxe.h | 26 RX_HIGH = DMA3
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/linux-4.4.14/arch/blackfin/mach-bf609/include/mach/ |
H A D | irq.h | 65 #define IRQ_SPORT1_RX BFIN_IRQ(49) /* SPORT1 RX Interrupt (DMA3) */
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H A D | defBF60x_base.h | 1581 DMA3 1583 #define DMA3_NEXT_DESC_PTR 0xFFC41180 /* DMA3 Pointer to Next Initial Descriptor */ 1584 #define DMA3_START_ADDR 0xFFC41184 /* DMA3 Start Address of Current Buffer */ 1585 #define DMA3_CONFIG 0xFFC41188 /* DMA3 Configuration Register */ 1586 #define DMA3_X_COUNT 0xFFC4118C /* DMA3 Inner Loop Count Start Value */ 1587 #define DMA3_X_MODIFY 0xFFC41190 /* DMA3 Inner Loop Address Increment */ 1588 #define DMA3_Y_COUNT 0xFFC41194 /* DMA3 Outer Loop Count Start Value (2D only) */ 1589 #define DMA3_Y_MODIFY 0xFFC41198 /* DMA3 Outer Loop Address Increment (2D only) */ 1590 #define DMA3_CURR_DESC_PTR 0xFFC411A4 /* DMA3 Current Descriptor Pointer */ 1591 #define DMA3_PREV_DESC_PTR 0xFFC411A8 /* DMA3 Previous Initial Descriptor Pointer */ 1592 #define DMA3_CURR_ADDR 0xFFC411AC /* DMA3 Current Address */ 1593 #define DMA3_IRQ_STATUS 0xFFC411B0 /* DMA3 Status Register */ 1594 #define DMA3_CURR_X_COUNT 0xFFC411B4 /* DMA3 Current Count(1D) or intra-row XCNT (2D) */ 1595 #define DMA3_CURR_Y_COUNT 0xFFC411B8 /* DMA3 Current Row Count (2D only) */ 1596 #define DMA3_BWL_COUNT 0xFFC411C0 /* DMA3 Bandwidth Limit Count */ 1597 #define DMA3_CURR_BWL_COUNT 0xFFC411C4 /* DMA3 Bandwidth Limit Count Current */ 1598 #define DMA3_BWM_COUNT 0xFFC411C8 /* DMA3 Bandwidth Monitor Count */ 1599 #define DMA3_CURR_BWM_COUNT 0xFFC411CC /* DMA3 Bandwidth Monitor Count Current */
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/linux-4.4.14/arch/m32r/include/asm/ |
H A D | m32102.h | 255 #define M32R_IRQ_DMA3 (35) /* DMA3 */
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/linux-4.4.14/drivers/media/i2c/ |
H A D | saa717x.c | 665 7-4: DMA2, 3-0: DMA1 ch. DMA4, DMA3 DMA2, DMA1
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/linux-4.4.14/arch/blackfin/mach-bf527/include/mach/ |
H A D | defBF525.h | 637 #define DMA3_INT 0x8 /* DMA3 pending interrupt */
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/linux-4.4.14/sound/pci/ice1712/ |
H A D | ice1724.c | 471 * Playback DMA3 = playback_con_substream_ds[2] snd_vt1724_interrupt()
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/linux-4.4.14/drivers/parport/ |
H A D | parport_pc.c | 1011 DMA_C=DMA3 (this is true e.g. for TYAN 1564D Tomcat IV) */ show_parconfig_smsc37c669()
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