Searched refs:ControllerBaseAddress (Results 1 - 2 of 2) sorted by relevance

/linux-4.4.14/drivers/block/
H A DDAC960.h2636 void DAC960_GEM_HardwareMailboxNewCommand(void __iomem *ControllerBaseAddress) DAC960_GEM_HardwareMailboxNewCommand() argument
2642 ControllerBaseAddress + DAC960_GEM_InboundDoorBellRegisterReadSetOffset); DAC960_GEM_HardwareMailboxNewCommand()
2646 void DAC960_GEM_AcknowledgeHardwareMailboxStatus(void __iomem *ControllerBaseAddress) DAC960_GEM_AcknowledgeHardwareMailboxStatus() argument
2652 ControllerBaseAddress + DAC960_GEM_InboundDoorBellRegisterClearOffset); DAC960_GEM_AcknowledgeHardwareMailboxStatus()
2656 void DAC960_GEM_GenerateInterrupt(void __iomem *ControllerBaseAddress) DAC960_GEM_GenerateInterrupt() argument
2662 ControllerBaseAddress + DAC960_GEM_InboundDoorBellRegisterReadSetOffset); DAC960_GEM_GenerateInterrupt()
2666 void DAC960_GEM_ControllerReset(void __iomem *ControllerBaseAddress) DAC960_GEM_ControllerReset() argument
2672 ControllerBaseAddress + DAC960_GEM_InboundDoorBellRegisterReadSetOffset); DAC960_GEM_ControllerReset()
2676 void DAC960_GEM_MemoryMailboxNewCommand(void __iomem *ControllerBaseAddress) DAC960_GEM_MemoryMailboxNewCommand() argument
2682 ControllerBaseAddress + DAC960_GEM_InboundDoorBellRegisterReadSetOffset); DAC960_GEM_MemoryMailboxNewCommand()
2686 bool DAC960_GEM_HardwareMailboxFullP(void __iomem *ControllerBaseAddress) DAC960_GEM_HardwareMailboxFullP() argument
2690 readl(ControllerBaseAddress + DAC960_GEM_HardwareMailboxFullP()
2696 bool DAC960_GEM_InitializationInProgressP(void __iomem *ControllerBaseAddress) DAC960_GEM_InitializationInProgressP() argument
2700 readl(ControllerBaseAddress + DAC960_GEM_InitializationInProgressP()
2706 void DAC960_GEM_AcknowledgeHardwareMailboxInterrupt(void __iomem *ControllerBaseAddress) DAC960_GEM_AcknowledgeHardwareMailboxInterrupt() argument
2712 ControllerBaseAddress + DAC960_GEM_OutboundDoorBellRegisterClearOffset); DAC960_GEM_AcknowledgeHardwareMailboxInterrupt()
2716 void DAC960_GEM_AcknowledgeMemoryMailboxInterrupt(void __iomem *ControllerBaseAddress) DAC960_GEM_AcknowledgeMemoryMailboxInterrupt() argument
2722 ControllerBaseAddress + DAC960_GEM_OutboundDoorBellRegisterClearOffset); DAC960_GEM_AcknowledgeMemoryMailboxInterrupt()
2726 void DAC960_GEM_AcknowledgeInterrupt(void __iomem *ControllerBaseAddress) DAC960_GEM_AcknowledgeInterrupt() argument
2733 ControllerBaseAddress + DAC960_GEM_OutboundDoorBellRegisterClearOffset); DAC960_GEM_AcknowledgeInterrupt()
2737 bool DAC960_GEM_HardwareMailboxStatusAvailableP(void __iomem *ControllerBaseAddress) DAC960_GEM_HardwareMailboxStatusAvailableP() argument
2741 readl(ControllerBaseAddress + DAC960_GEM_HardwareMailboxStatusAvailableP()
2747 bool DAC960_GEM_MemoryMailboxStatusAvailableP(void __iomem *ControllerBaseAddress) DAC960_GEM_MemoryMailboxStatusAvailableP() argument
2751 readl(ControllerBaseAddress + DAC960_GEM_MemoryMailboxStatusAvailableP()
2757 void DAC960_GEM_EnableInterrupts(void __iomem *ControllerBaseAddress) DAC960_GEM_EnableInterrupts() argument
2764 ControllerBaseAddress + DAC960_GEM_InterruptMaskRegisterClearOffset); DAC960_GEM_EnableInterrupts()
2768 void DAC960_GEM_DisableInterrupts(void __iomem *ControllerBaseAddress) DAC960_GEM_DisableInterrupts() argument
2775 ControllerBaseAddress + DAC960_GEM_InterruptMaskRegisterReadSetOffset); DAC960_GEM_DisableInterrupts()
2779 bool DAC960_GEM_InterruptsEnabledP(void __iomem *ControllerBaseAddress) DAC960_GEM_InterruptsEnabledP() argument
2783 readl(ControllerBaseAddress + DAC960_GEM_InterruptsEnabledP()
2803 void DAC960_GEM_WriteHardwareMailbox(void __iomem *ControllerBaseAddress, DAC960_GEM_WriteHardwareMailbox() argument
2807 ControllerBaseAddress + DAC960_GEM_WriteHardwareMailbox()
2812 DAC960_GEM_ReadCommandIdentifier(void __iomem *ControllerBaseAddress) DAC960_GEM_ReadCommandIdentifier() argument
2814 return readw(ControllerBaseAddress + DAC960_GEM_CommandStatusOffset); DAC960_GEM_ReadCommandIdentifier()
2818 DAC960_GEM_ReadCommandStatus(void __iomem *ControllerBaseAddress) DAC960_GEM_ReadCommandStatus() argument
2820 return readw(ControllerBaseAddress + DAC960_GEM_CommandStatusOffset + 2); DAC960_GEM_ReadCommandStatus()
2824 DAC960_GEM_ReadErrorStatus(void __iomem *ControllerBaseAddress, DAC960_GEM_ReadErrorStatus() argument
2831 readl(ControllerBaseAddress + DAC960_GEM_ErrorStatusRegisterReadSetOffset); DAC960_GEM_ReadErrorStatus()
2836 readb(ControllerBaseAddress + DAC960_GEM_CommandMailboxBusAddressOffset + 0); DAC960_GEM_ReadErrorStatus()
2838 readb(ControllerBaseAddress + DAC960_GEM_CommandMailboxBusAddressOffset + 1); DAC960_GEM_ReadErrorStatus()
2839 writel(0x03000000, ControllerBaseAddress + DAC960_GEM_ReadErrorStatus()
2947 void DAC960_BA_HardwareMailboxNewCommand(void __iomem *ControllerBaseAddress) DAC960_BA_HardwareMailboxNewCommand() argument
2953 ControllerBaseAddress + DAC960_BA_InboundDoorBellRegisterOffset); DAC960_BA_HardwareMailboxNewCommand()
2957 void DAC960_BA_AcknowledgeHardwareMailboxStatus(void __iomem *ControllerBaseAddress) DAC960_BA_AcknowledgeHardwareMailboxStatus() argument
2963 ControllerBaseAddress + DAC960_BA_InboundDoorBellRegisterOffset); DAC960_BA_AcknowledgeHardwareMailboxStatus()
2967 void DAC960_BA_GenerateInterrupt(void __iomem *ControllerBaseAddress) DAC960_BA_GenerateInterrupt() argument
2973 ControllerBaseAddress + DAC960_BA_InboundDoorBellRegisterOffset); DAC960_BA_GenerateInterrupt()
2977 void DAC960_BA_ControllerReset(void __iomem *ControllerBaseAddress) DAC960_BA_ControllerReset() argument
2983 ControllerBaseAddress + DAC960_BA_InboundDoorBellRegisterOffset); DAC960_BA_ControllerReset()
2987 void DAC960_BA_MemoryMailboxNewCommand(void __iomem *ControllerBaseAddress) DAC960_BA_MemoryMailboxNewCommand() argument
2993 ControllerBaseAddress + DAC960_BA_InboundDoorBellRegisterOffset); DAC960_BA_MemoryMailboxNewCommand()
2997 bool DAC960_BA_HardwareMailboxFullP(void __iomem *ControllerBaseAddress) DAC960_BA_HardwareMailboxFullP() argument
3001 readb(ControllerBaseAddress + DAC960_BA_InboundDoorBellRegisterOffset); DAC960_BA_HardwareMailboxFullP()
3006 bool DAC960_BA_InitializationInProgressP(void __iomem *ControllerBaseAddress) DAC960_BA_InitializationInProgressP() argument
3010 readb(ControllerBaseAddress + DAC960_BA_InboundDoorBellRegisterOffset); DAC960_BA_InitializationInProgressP()
3015 void DAC960_BA_AcknowledgeHardwareMailboxInterrupt(void __iomem *ControllerBaseAddress) DAC960_BA_AcknowledgeHardwareMailboxInterrupt() argument
3021 ControllerBaseAddress + DAC960_BA_OutboundDoorBellRegisterOffset); DAC960_BA_AcknowledgeHardwareMailboxInterrupt()
3025 void DAC960_BA_AcknowledgeMemoryMailboxInterrupt(void __iomem *ControllerBaseAddress) DAC960_BA_AcknowledgeMemoryMailboxInterrupt() argument
3031 ControllerBaseAddress + DAC960_BA_OutboundDoorBellRegisterOffset); DAC960_BA_AcknowledgeMemoryMailboxInterrupt()
3035 void DAC960_BA_AcknowledgeInterrupt(void __iomem *ControllerBaseAddress) DAC960_BA_AcknowledgeInterrupt() argument
3042 ControllerBaseAddress + DAC960_BA_OutboundDoorBellRegisterOffset); DAC960_BA_AcknowledgeInterrupt()
3046 bool DAC960_BA_HardwareMailboxStatusAvailableP(void __iomem *ControllerBaseAddress) DAC960_BA_HardwareMailboxStatusAvailableP() argument
3050 readb(ControllerBaseAddress + DAC960_BA_OutboundDoorBellRegisterOffset); DAC960_BA_HardwareMailboxStatusAvailableP()
3055 bool DAC960_BA_MemoryMailboxStatusAvailableP(void __iomem *ControllerBaseAddress) DAC960_BA_MemoryMailboxStatusAvailableP() argument
3059 readb(ControllerBaseAddress + DAC960_BA_OutboundDoorBellRegisterOffset); DAC960_BA_MemoryMailboxStatusAvailableP()
3064 void DAC960_BA_EnableInterrupts(void __iomem *ControllerBaseAddress) DAC960_BA_EnableInterrupts() argument
3071 ControllerBaseAddress + DAC960_BA_InterruptMaskRegisterOffset); DAC960_BA_EnableInterrupts()
3075 void DAC960_BA_DisableInterrupts(void __iomem *ControllerBaseAddress) DAC960_BA_DisableInterrupts() argument
3082 ControllerBaseAddress + DAC960_BA_InterruptMaskRegisterOffset); DAC960_BA_DisableInterrupts()
3086 bool DAC960_BA_InterruptsEnabledP(void __iomem *ControllerBaseAddress) DAC960_BA_InterruptsEnabledP() argument
3090 readb(ControllerBaseAddress + DAC960_BA_InterruptMaskRegisterOffset); DAC960_BA_InterruptsEnabledP()
3109 void DAC960_BA_WriteHardwareMailbox(void __iomem *ControllerBaseAddress, DAC960_BA_WriteHardwareMailbox() argument
3113 ControllerBaseAddress + DAC960_BA_WriteHardwareMailbox()
3118 DAC960_BA_ReadCommandIdentifier(void __iomem *ControllerBaseAddress) DAC960_BA_ReadCommandIdentifier() argument
3120 return readw(ControllerBaseAddress + DAC960_BA_CommandStatusOffset); DAC960_BA_ReadCommandIdentifier()
3124 DAC960_BA_ReadCommandStatus(void __iomem *ControllerBaseAddress) DAC960_BA_ReadCommandStatus() argument
3126 return readw(ControllerBaseAddress + DAC960_BA_CommandStatusOffset + 2); DAC960_BA_ReadCommandStatus()
3130 DAC960_BA_ReadErrorStatus(void __iomem *ControllerBaseAddress, DAC960_BA_ReadErrorStatus() argument
3137 readb(ControllerBaseAddress + DAC960_BA_ErrorStatusRegisterOffset); DAC960_BA_ReadErrorStatus()
3142 readb(ControllerBaseAddress + DAC960_BA_CommandMailboxBusAddressOffset + 0); DAC960_BA_ReadErrorStatus()
3144 readb(ControllerBaseAddress + DAC960_BA_CommandMailboxBusAddressOffset + 1); DAC960_BA_ReadErrorStatus()
3145 writeb(0xFF, ControllerBaseAddress + DAC960_BA_ErrorStatusRegisterOffset); DAC960_BA_ReadErrorStatus()
3252 void DAC960_LP_HardwareMailboxNewCommand(void __iomem *ControllerBaseAddress) DAC960_LP_HardwareMailboxNewCommand() argument
3258 ControllerBaseAddress + DAC960_LP_InboundDoorBellRegisterOffset); DAC960_LP_HardwareMailboxNewCommand()
3262 void DAC960_LP_AcknowledgeHardwareMailboxStatus(void __iomem *ControllerBaseAddress) DAC960_LP_AcknowledgeHardwareMailboxStatus() argument
3268 ControllerBaseAddress + DAC960_LP_InboundDoorBellRegisterOffset); DAC960_LP_AcknowledgeHardwareMailboxStatus()
3272 void DAC960_LP_GenerateInterrupt(void __iomem *ControllerBaseAddress) DAC960_LP_GenerateInterrupt() argument
3278 ControllerBaseAddress + DAC960_LP_InboundDoorBellRegisterOffset); DAC960_LP_GenerateInterrupt()
3282 void DAC960_LP_ControllerReset(void __iomem *ControllerBaseAddress) DAC960_LP_ControllerReset() argument
3288 ControllerBaseAddress + DAC960_LP_InboundDoorBellRegisterOffset); DAC960_LP_ControllerReset()
3292 void DAC960_LP_MemoryMailboxNewCommand(void __iomem *ControllerBaseAddress) DAC960_LP_MemoryMailboxNewCommand() argument
3298 ControllerBaseAddress + DAC960_LP_InboundDoorBellRegisterOffset); DAC960_LP_MemoryMailboxNewCommand()
3302 bool DAC960_LP_HardwareMailboxFullP(void __iomem *ControllerBaseAddress) DAC960_LP_HardwareMailboxFullP() argument
3306 readb(ControllerBaseAddress + DAC960_LP_InboundDoorBellRegisterOffset); DAC960_LP_HardwareMailboxFullP()
3311 bool DAC960_LP_InitializationInProgressP(void __iomem *ControllerBaseAddress) DAC960_LP_InitializationInProgressP() argument
3315 readb(ControllerBaseAddress + DAC960_LP_InboundDoorBellRegisterOffset); DAC960_LP_InitializationInProgressP()
3320 void DAC960_LP_AcknowledgeHardwareMailboxInterrupt(void __iomem *ControllerBaseAddress) DAC960_LP_AcknowledgeHardwareMailboxInterrupt() argument
3326 ControllerBaseAddress + DAC960_LP_OutboundDoorBellRegisterOffset); DAC960_LP_AcknowledgeHardwareMailboxInterrupt()
3330 void DAC960_LP_AcknowledgeMemoryMailboxInterrupt(void __iomem *ControllerBaseAddress) DAC960_LP_AcknowledgeMemoryMailboxInterrupt() argument
3336 ControllerBaseAddress + DAC960_LP_OutboundDoorBellRegisterOffset); DAC960_LP_AcknowledgeMemoryMailboxInterrupt()
3340 void DAC960_LP_AcknowledgeInterrupt(void __iomem *ControllerBaseAddress) DAC960_LP_AcknowledgeInterrupt() argument
3347 ControllerBaseAddress + DAC960_LP_OutboundDoorBellRegisterOffset); DAC960_LP_AcknowledgeInterrupt()
3351 bool DAC960_LP_HardwareMailboxStatusAvailableP(void __iomem *ControllerBaseAddress) DAC960_LP_HardwareMailboxStatusAvailableP() argument
3355 readb(ControllerBaseAddress + DAC960_LP_OutboundDoorBellRegisterOffset); DAC960_LP_HardwareMailboxStatusAvailableP()
3360 bool DAC960_LP_MemoryMailboxStatusAvailableP(void __iomem *ControllerBaseAddress) DAC960_LP_MemoryMailboxStatusAvailableP() argument
3364 readb(ControllerBaseAddress + DAC960_LP_OutboundDoorBellRegisterOffset); DAC960_LP_MemoryMailboxStatusAvailableP()
3369 void DAC960_LP_EnableInterrupts(void __iomem *ControllerBaseAddress) DAC960_LP_EnableInterrupts() argument
3375 ControllerBaseAddress + DAC960_LP_InterruptMaskRegisterOffset); DAC960_LP_EnableInterrupts()
3379 void DAC960_LP_DisableInterrupts(void __iomem *ControllerBaseAddress) DAC960_LP_DisableInterrupts() argument
3385 ControllerBaseAddress + DAC960_LP_InterruptMaskRegisterOffset); DAC960_LP_DisableInterrupts()
3389 bool DAC960_LP_InterruptsEnabledP(void __iomem *ControllerBaseAddress) DAC960_LP_InterruptsEnabledP() argument
3393 readb(ControllerBaseAddress + DAC960_LP_InterruptMaskRegisterOffset); DAC960_LP_InterruptsEnabledP()
3411 void DAC960_LP_WriteHardwareMailbox(void __iomem *ControllerBaseAddress, DAC960_LP_WriteHardwareMailbox() argument
3415 ControllerBaseAddress + DAC960_LP_WriteHardwareMailbox()
3420 DAC960_LP_ReadCommandIdentifier(void __iomem *ControllerBaseAddress) DAC960_LP_ReadCommandIdentifier() argument
3422 return readw(ControllerBaseAddress + DAC960_LP_CommandStatusOffset); DAC960_LP_ReadCommandIdentifier()
3426 DAC960_LP_ReadCommandStatus(void __iomem *ControllerBaseAddress) DAC960_LP_ReadCommandStatus() argument
3428 return readw(ControllerBaseAddress + DAC960_LP_CommandStatusOffset + 2); DAC960_LP_ReadCommandStatus()
3432 DAC960_LP_ReadErrorStatus(void __iomem *ControllerBaseAddress, DAC960_LP_ReadErrorStatus() argument
3439 readb(ControllerBaseAddress + DAC960_LP_ErrorStatusRegisterOffset); DAC960_LP_ReadErrorStatus()
3444 readb(ControllerBaseAddress + DAC960_LP_CommandMailboxBusAddressOffset + 0); DAC960_LP_ReadErrorStatus()
3446 readb(ControllerBaseAddress + DAC960_LP_CommandMailboxBusAddressOffset + 1); DAC960_LP_ReadErrorStatus()
3447 writeb(0xFF, ControllerBaseAddress + DAC960_LP_ErrorStatusRegisterOffset); DAC960_LP_ReadErrorStatus()
3566 void DAC960_LA_HardwareMailboxNewCommand(void __iomem *ControllerBaseAddress) DAC960_LA_HardwareMailboxNewCommand() argument
3572 ControllerBaseAddress + DAC960_LA_InboundDoorBellRegisterOffset); DAC960_LA_HardwareMailboxNewCommand()
3576 void DAC960_LA_AcknowledgeHardwareMailboxStatus(void __iomem *ControllerBaseAddress) DAC960_LA_AcknowledgeHardwareMailboxStatus() argument
3582 ControllerBaseAddress + DAC960_LA_InboundDoorBellRegisterOffset); DAC960_LA_AcknowledgeHardwareMailboxStatus()
3586 void DAC960_LA_GenerateInterrupt(void __iomem *ControllerBaseAddress) DAC960_LA_GenerateInterrupt() argument
3592 ControllerBaseAddress + DAC960_LA_InboundDoorBellRegisterOffset); DAC960_LA_GenerateInterrupt()
3596 void DAC960_LA_ControllerReset(void __iomem *ControllerBaseAddress) DAC960_LA_ControllerReset() argument
3602 ControllerBaseAddress + DAC960_LA_InboundDoorBellRegisterOffset); DAC960_LA_ControllerReset()
3606 void DAC960_LA_MemoryMailboxNewCommand(void __iomem *ControllerBaseAddress) DAC960_LA_MemoryMailboxNewCommand() argument
3612 ControllerBaseAddress + DAC960_LA_InboundDoorBellRegisterOffset); DAC960_LA_MemoryMailboxNewCommand()
3616 bool DAC960_LA_HardwareMailboxFullP(void __iomem *ControllerBaseAddress) DAC960_LA_HardwareMailboxFullP() argument
3620 readb(ControllerBaseAddress + DAC960_LA_InboundDoorBellRegisterOffset); DAC960_LA_HardwareMailboxFullP()
3625 bool DAC960_LA_InitializationInProgressP(void __iomem *ControllerBaseAddress) DAC960_LA_InitializationInProgressP() argument
3629 readb(ControllerBaseAddress + DAC960_LA_InboundDoorBellRegisterOffset); DAC960_LA_InitializationInProgressP()
3634 void DAC960_LA_AcknowledgeHardwareMailboxInterrupt(void __iomem *ControllerBaseAddress) DAC960_LA_AcknowledgeHardwareMailboxInterrupt() argument
3640 ControllerBaseAddress + DAC960_LA_OutboundDoorBellRegisterOffset); DAC960_LA_AcknowledgeHardwareMailboxInterrupt()
3644 void DAC960_LA_AcknowledgeMemoryMailboxInterrupt(void __iomem *ControllerBaseAddress) DAC960_LA_AcknowledgeMemoryMailboxInterrupt() argument
3650 ControllerBaseAddress + DAC960_LA_OutboundDoorBellRegisterOffset); DAC960_LA_AcknowledgeMemoryMailboxInterrupt()
3654 void DAC960_LA_AcknowledgeInterrupt(void __iomem *ControllerBaseAddress) DAC960_LA_AcknowledgeInterrupt() argument
3661 ControllerBaseAddress + DAC960_LA_OutboundDoorBellRegisterOffset); DAC960_LA_AcknowledgeInterrupt()
3665 bool DAC960_LA_HardwareMailboxStatusAvailableP(void __iomem *ControllerBaseAddress) DAC960_LA_HardwareMailboxStatusAvailableP() argument
3669 readb(ControllerBaseAddress + DAC960_LA_OutboundDoorBellRegisterOffset); DAC960_LA_HardwareMailboxStatusAvailableP()
3674 bool DAC960_LA_MemoryMailboxStatusAvailableP(void __iomem *ControllerBaseAddress) DAC960_LA_MemoryMailboxStatusAvailableP() argument
3678 readb(ControllerBaseAddress + DAC960_LA_OutboundDoorBellRegisterOffset); DAC960_LA_MemoryMailboxStatusAvailableP()
3683 void DAC960_LA_EnableInterrupts(void __iomem *ControllerBaseAddress) DAC960_LA_EnableInterrupts() argument
3689 ControllerBaseAddress + DAC960_LA_InterruptMaskRegisterOffset); DAC960_LA_EnableInterrupts()
3693 void DAC960_LA_DisableInterrupts(void __iomem *ControllerBaseAddress) DAC960_LA_DisableInterrupts() argument
3699 ControllerBaseAddress + DAC960_LA_InterruptMaskRegisterOffset); DAC960_LA_DisableInterrupts()
3703 bool DAC960_LA_InterruptsEnabledP(void __iomem *ControllerBaseAddress) DAC960_LA_InterruptsEnabledP() argument
3707 readb(ControllerBaseAddress + DAC960_LA_InterruptMaskRegisterOffset); DAC960_LA_InterruptsEnabledP()
3726 void DAC960_LA_WriteHardwareMailbox(void __iomem *ControllerBaseAddress, DAC960_LA_WriteHardwareMailbox() argument
3730 ControllerBaseAddress + DAC960_LA_CommandOpcodeRegisterOffset); DAC960_LA_WriteHardwareMailbox()
3732 ControllerBaseAddress + DAC960_LA_MailboxRegister4Offset); DAC960_LA_WriteHardwareMailbox()
3734 ControllerBaseAddress + DAC960_LA_MailboxRegister8Offset); DAC960_LA_WriteHardwareMailbox()
3736 ControllerBaseAddress + DAC960_LA_MailboxRegister12Offset); DAC960_LA_WriteHardwareMailbox()
3740 DAC960_LA_ReadStatusCommandIdentifier(void __iomem *ControllerBaseAddress) DAC960_LA_ReadStatusCommandIdentifier() argument
3742 return readb(ControllerBaseAddress DAC960_LA_ReadStatusCommandIdentifier()
3747 DAC960_LA_ReadStatusRegister(void __iomem *ControllerBaseAddress) DAC960_LA_ReadStatusRegister() argument
3749 return readw(ControllerBaseAddress + DAC960_LA_StatusRegisterOffset); DAC960_LA_ReadStatusRegister()
3753 DAC960_LA_ReadErrorStatus(void __iomem *ControllerBaseAddress, DAC960_LA_ReadErrorStatus() argument
3760 readb(ControllerBaseAddress + DAC960_LA_ErrorStatusRegisterOffset); DAC960_LA_ReadErrorStatus()
3765 readb(ControllerBaseAddress + DAC960_LA_CommandOpcodeRegisterOffset); DAC960_LA_ReadErrorStatus()
3767 readb(ControllerBaseAddress + DAC960_LA_CommandIdentifierRegisterOffset); DAC960_LA_ReadErrorStatus()
3768 writeb(0xFF, ControllerBaseAddress + DAC960_LA_ErrorStatusRegisterOffset); DAC960_LA_ReadErrorStatus()
3887 void DAC960_PG_HardwareMailboxNewCommand(void __iomem *ControllerBaseAddress) DAC960_PG_HardwareMailboxNewCommand() argument
3893 ControllerBaseAddress + DAC960_PG_InboundDoorBellRegisterOffset); DAC960_PG_HardwareMailboxNewCommand()
3897 void DAC960_PG_AcknowledgeHardwareMailboxStatus(void __iomem *ControllerBaseAddress) DAC960_PG_AcknowledgeHardwareMailboxStatus() argument
3903 ControllerBaseAddress + DAC960_PG_InboundDoorBellRegisterOffset); DAC960_PG_AcknowledgeHardwareMailboxStatus()
3907 void DAC960_PG_GenerateInterrupt(void __iomem *ControllerBaseAddress) DAC960_PG_GenerateInterrupt() argument
3913 ControllerBaseAddress + DAC960_PG_InboundDoorBellRegisterOffset); DAC960_PG_GenerateInterrupt()
3917 void DAC960_PG_ControllerReset(void __iomem *ControllerBaseAddress) DAC960_PG_ControllerReset() argument
3923 ControllerBaseAddress + DAC960_PG_InboundDoorBellRegisterOffset); DAC960_PG_ControllerReset()
3927 void DAC960_PG_MemoryMailboxNewCommand(void __iomem *ControllerBaseAddress) DAC960_PG_MemoryMailboxNewCommand() argument
3933 ControllerBaseAddress + DAC960_PG_InboundDoorBellRegisterOffset); DAC960_PG_MemoryMailboxNewCommand()
3937 bool DAC960_PG_HardwareMailboxFullP(void __iomem *ControllerBaseAddress) DAC960_PG_HardwareMailboxFullP() argument
3941 readl(ControllerBaseAddress + DAC960_PG_InboundDoorBellRegisterOffset); DAC960_PG_HardwareMailboxFullP()
3946 bool DAC960_PG_InitializationInProgressP(void __iomem *ControllerBaseAddress) DAC960_PG_InitializationInProgressP() argument
3950 readl(ControllerBaseAddress + DAC960_PG_InboundDoorBellRegisterOffset); DAC960_PG_InitializationInProgressP()
3955 void DAC960_PG_AcknowledgeHardwareMailboxInterrupt(void __iomem *ControllerBaseAddress) DAC960_PG_AcknowledgeHardwareMailboxInterrupt() argument
3961 ControllerBaseAddress + DAC960_PG_OutboundDoorBellRegisterOffset); DAC960_PG_AcknowledgeHardwareMailboxInterrupt()
3965 void DAC960_PG_AcknowledgeMemoryMailboxInterrupt(void __iomem *ControllerBaseAddress) DAC960_PG_AcknowledgeMemoryMailboxInterrupt() argument
3971 ControllerBaseAddress + DAC960_PG_OutboundDoorBellRegisterOffset); DAC960_PG_AcknowledgeMemoryMailboxInterrupt()
3975 void DAC960_PG_AcknowledgeInterrupt(void __iomem *ControllerBaseAddress) DAC960_PG_AcknowledgeInterrupt() argument
3982 ControllerBaseAddress + DAC960_PG_OutboundDoorBellRegisterOffset); DAC960_PG_AcknowledgeInterrupt()
3986 bool DAC960_PG_HardwareMailboxStatusAvailableP(void __iomem *ControllerBaseAddress) DAC960_PG_HardwareMailboxStatusAvailableP() argument
3990 readl(ControllerBaseAddress + DAC960_PG_OutboundDoorBellRegisterOffset); DAC960_PG_HardwareMailboxStatusAvailableP()
3995 bool DAC960_PG_MemoryMailboxStatusAvailableP(void __iomem *ControllerBaseAddress) DAC960_PG_MemoryMailboxStatusAvailableP() argument
3999 readl(ControllerBaseAddress + DAC960_PG_OutboundDoorBellRegisterOffset); DAC960_PG_MemoryMailboxStatusAvailableP()
4004 void DAC960_PG_EnableInterrupts(void __iomem *ControllerBaseAddress) DAC960_PG_EnableInterrupts() argument
4012 ControllerBaseAddress + DAC960_PG_InterruptMaskRegisterOffset); DAC960_PG_EnableInterrupts()
4016 void DAC960_PG_DisableInterrupts(void __iomem *ControllerBaseAddress) DAC960_PG_DisableInterrupts() argument
4024 ControllerBaseAddress + DAC960_PG_InterruptMaskRegisterOffset); DAC960_PG_DisableInterrupts()
4028 bool DAC960_PG_InterruptsEnabledP(void __iomem *ControllerBaseAddress) DAC960_PG_InterruptsEnabledP() argument
4032 readl(ControllerBaseAddress + DAC960_PG_InterruptMaskRegisterOffset); DAC960_PG_InterruptsEnabledP()
4051 void DAC960_PG_WriteHardwareMailbox(void __iomem *ControllerBaseAddress, DAC960_PG_WriteHardwareMailbox() argument
4055 ControllerBaseAddress + DAC960_PG_CommandOpcodeRegisterOffset); DAC960_PG_WriteHardwareMailbox()
4057 ControllerBaseAddress + DAC960_PG_MailboxRegister4Offset); DAC960_PG_WriteHardwareMailbox()
4059 ControllerBaseAddress + DAC960_PG_MailboxRegister8Offset); DAC960_PG_WriteHardwareMailbox()
4061 ControllerBaseAddress + DAC960_PG_MailboxRegister12Offset); DAC960_PG_WriteHardwareMailbox()
4065 DAC960_PG_ReadStatusCommandIdentifier(void __iomem *ControllerBaseAddress) DAC960_PG_ReadStatusCommandIdentifier() argument
4067 return readb(ControllerBaseAddress DAC960_PG_ReadStatusCommandIdentifier()
4072 DAC960_PG_ReadStatusRegister(void __iomem *ControllerBaseAddress) DAC960_PG_ReadStatusRegister() argument
4074 return readw(ControllerBaseAddress + DAC960_PG_StatusRegisterOffset); DAC960_PG_ReadStatusRegister()
4078 DAC960_PG_ReadErrorStatus(void __iomem *ControllerBaseAddress, DAC960_PG_ReadErrorStatus() argument
4085 readb(ControllerBaseAddress + DAC960_PG_ErrorStatusRegisterOffset); DAC960_PG_ReadErrorStatus()
4090 readb(ControllerBaseAddress + DAC960_PG_CommandOpcodeRegisterOffset); DAC960_PG_ReadErrorStatus()
4092 readb(ControllerBaseAddress + DAC960_PG_CommandIdentifierRegisterOffset); DAC960_PG_ReadErrorStatus()
4093 writeb(0, ControllerBaseAddress + DAC960_PG_ErrorStatusRegisterOffset); DAC960_PG_ReadErrorStatus()
4207 void DAC960_PD_NewCommand(void __iomem *ControllerBaseAddress) DAC960_PD_NewCommand() argument
4213 ControllerBaseAddress + DAC960_PD_InboundDoorBellRegisterOffset); DAC960_PD_NewCommand()
4217 void DAC960_PD_AcknowledgeStatus(void __iomem *ControllerBaseAddress) DAC960_PD_AcknowledgeStatus() argument
4223 ControllerBaseAddress + DAC960_PD_InboundDoorBellRegisterOffset); DAC960_PD_AcknowledgeStatus()
4227 void DAC960_PD_GenerateInterrupt(void __iomem *ControllerBaseAddress) DAC960_PD_GenerateInterrupt() argument
4233 ControllerBaseAddress + DAC960_PD_InboundDoorBellRegisterOffset); DAC960_PD_GenerateInterrupt()
4237 void DAC960_PD_ControllerReset(void __iomem *ControllerBaseAddress) DAC960_PD_ControllerReset() argument
4243 ControllerBaseAddress + DAC960_PD_InboundDoorBellRegisterOffset); DAC960_PD_ControllerReset()
4247 bool DAC960_PD_MailboxFullP(void __iomem *ControllerBaseAddress) DAC960_PD_MailboxFullP() argument
4251 readb(ControllerBaseAddress + DAC960_PD_InboundDoorBellRegisterOffset); DAC960_PD_MailboxFullP()
4256 bool DAC960_PD_InitializationInProgressP(void __iomem *ControllerBaseAddress) DAC960_PD_InitializationInProgressP() argument
4260 readb(ControllerBaseAddress + DAC960_PD_InboundDoorBellRegisterOffset); DAC960_PD_InitializationInProgressP()
4265 void DAC960_PD_AcknowledgeInterrupt(void __iomem *ControllerBaseAddress) DAC960_PD_AcknowledgeInterrupt() argument
4271 ControllerBaseAddress + DAC960_PD_OutboundDoorBellRegisterOffset); DAC960_PD_AcknowledgeInterrupt()
4275 bool DAC960_PD_StatusAvailableP(void __iomem *ControllerBaseAddress) DAC960_PD_StatusAvailableP() argument
4279 readb(ControllerBaseAddress + DAC960_PD_OutboundDoorBellRegisterOffset); DAC960_PD_StatusAvailableP()
4284 void DAC960_PD_EnableInterrupts(void __iomem *ControllerBaseAddress) DAC960_PD_EnableInterrupts() argument
4290 ControllerBaseAddress + DAC960_PD_InterruptEnableRegisterOffset); DAC960_PD_EnableInterrupts()
4294 void DAC960_PD_DisableInterrupts(void __iomem *ControllerBaseAddress) DAC960_PD_DisableInterrupts() argument
4300 ControllerBaseAddress + DAC960_PD_InterruptEnableRegisterOffset); DAC960_PD_DisableInterrupts()
4304 bool DAC960_PD_InterruptsEnabledP(void __iomem *ControllerBaseAddress) DAC960_PD_InterruptsEnabledP() argument
4308 readb(ControllerBaseAddress + DAC960_PD_InterruptEnableRegisterOffset); DAC960_PD_InterruptsEnabledP()
4313 void DAC960_PD_WriteCommandMailbox(void __iomem *ControllerBaseAddress, DAC960_PD_WriteCommandMailbox() argument
4317 ControllerBaseAddress + DAC960_PD_CommandOpcodeRegisterOffset); DAC960_PD_WriteCommandMailbox()
4319 ControllerBaseAddress + DAC960_PD_MailboxRegister4Offset); DAC960_PD_WriteCommandMailbox()
4321 ControllerBaseAddress + DAC960_PD_MailboxRegister8Offset); DAC960_PD_WriteCommandMailbox()
4323 ControllerBaseAddress + DAC960_PD_MailboxRegister12Offset); DAC960_PD_WriteCommandMailbox()
4327 DAC960_PD_ReadStatusCommandIdentifier(void __iomem *ControllerBaseAddress) DAC960_PD_ReadStatusCommandIdentifier() argument
4329 return readb(ControllerBaseAddress DAC960_PD_ReadStatusCommandIdentifier()
4334 DAC960_PD_ReadStatusRegister(void __iomem *ControllerBaseAddress) DAC960_PD_ReadStatusRegister() argument
4336 return readw(ControllerBaseAddress + DAC960_PD_StatusRegisterOffset); DAC960_PD_ReadStatusRegister()
4340 DAC960_PD_ReadErrorStatus(void __iomem *ControllerBaseAddress, DAC960_PD_ReadErrorStatus() argument
4347 readb(ControllerBaseAddress + DAC960_PD_ErrorStatusRegisterOffset); DAC960_PD_ReadErrorStatus()
4352 readb(ControllerBaseAddress + DAC960_PD_CommandOpcodeRegisterOffset); DAC960_PD_ReadErrorStatus()
4354 readb(ControllerBaseAddress + DAC960_PD_CommandIdentifierRegisterOffset); DAC960_PD_ReadErrorStatus()
4355 writeb(0, ControllerBaseAddress + DAC960_PD_ErrorStatusRegisterOffset); DAC960_PD_ReadErrorStatus()
H A DDAC960.c540 void __iomem *ControllerBaseAddress = Controller->BaseAddress; DAC960_GEM_QueueCommand() local
550 DAC960_GEM_MemoryMailboxNewCommand(ControllerBaseAddress); DAC960_GEM_QueueCommand()
569 void __iomem *ControllerBaseAddress = Controller->BaseAddress; DAC960_BA_QueueCommand() local
577 DAC960_BA_MemoryMailboxNewCommand(ControllerBaseAddress); DAC960_BA_QueueCommand()
594 void __iomem *ControllerBaseAddress = Controller->BaseAddress; DAC960_LP_QueueCommand() local
602 DAC960_LP_MemoryMailboxNewCommand(ControllerBaseAddress); DAC960_LP_QueueCommand()
620 void __iomem *ControllerBaseAddress = Controller->BaseAddress; DAC960_LA_QueueCommandDualMode() local
628 DAC960_LA_MemoryMailboxNewCommand(ControllerBaseAddress); DAC960_LA_QueueCommandDualMode()
646 void __iomem *ControllerBaseAddress = Controller->BaseAddress; DAC960_LA_QueueCommandSingleMode() local
654 DAC960_LA_HardwareMailboxNewCommand(ControllerBaseAddress); DAC960_LA_QueueCommandSingleMode()
672 void __iomem *ControllerBaseAddress = Controller->BaseAddress; DAC960_PG_QueueCommandDualMode() local
680 DAC960_PG_MemoryMailboxNewCommand(ControllerBaseAddress); DAC960_PG_QueueCommandDualMode()
698 void __iomem *ControllerBaseAddress = Controller->BaseAddress; DAC960_PG_QueueCommandSingleMode() local
706 DAC960_PG_HardwareMailboxNewCommand(ControllerBaseAddress); DAC960_PG_QueueCommandSingleMode()
723 void __iomem *ControllerBaseAddress = Controller->BaseAddress; DAC960_PD_QueueCommand() local
726 while (DAC960_PD_MailboxFullP(ControllerBaseAddress)) DAC960_PD_QueueCommand()
728 DAC960_PD_WriteCommandMailbox(ControllerBaseAddress, CommandMailbox); DAC960_PD_QueueCommand()
729 DAC960_PD_NewCommand(ControllerBaseAddress); DAC960_PD_QueueCommand()
740 void __iomem *ControllerBaseAddress = Controller->BaseAddress; DAC960_P_QueueCommand() local
772 while (DAC960_PD_MailboxFullP(ControllerBaseAddress)) DAC960_P_QueueCommand()
774 DAC960_PD_WriteCommandMailbox(ControllerBaseAddress, CommandMailbox); DAC960_P_QueueCommand()
775 DAC960_PD_NewCommand(ControllerBaseAddress); DAC960_P_QueueCommand()
1161 void __iomem *ControllerBaseAddress = Controller->BaseAddress; DAC960_V1_EnableMemoryMailboxInterface() local
1295 if (!DAC960_LA_HardwareMailboxFullP(ControllerBaseAddress)) DAC960_V1_EnableMemoryMailboxInterface()
1300 DAC960_LA_WriteHardwareMailbox(ControllerBaseAddress, &CommandMailbox); DAC960_V1_EnableMemoryMailboxInterface()
1301 DAC960_LA_HardwareMailboxNewCommand(ControllerBaseAddress); DAC960_V1_EnableMemoryMailboxInterface()
1306 ControllerBaseAddress)) DAC960_V1_EnableMemoryMailboxInterface()
1311 CommandStatus = DAC960_LA_ReadStatusRegister(ControllerBaseAddress); DAC960_V1_EnableMemoryMailboxInterface()
1312 DAC960_LA_AcknowledgeHardwareMailboxInterrupt(ControllerBaseAddress); DAC960_V1_EnableMemoryMailboxInterface()
1313 DAC960_LA_AcknowledgeHardwareMailboxStatus(ControllerBaseAddress); DAC960_V1_EnableMemoryMailboxInterface()
1322 if (!DAC960_PG_HardwareMailboxFullP(ControllerBaseAddress)) DAC960_V1_EnableMemoryMailboxInterface()
1327 DAC960_PG_WriteHardwareMailbox(ControllerBaseAddress, &CommandMailbox); DAC960_V1_EnableMemoryMailboxInterface()
1328 DAC960_PG_HardwareMailboxNewCommand(ControllerBaseAddress); DAC960_V1_EnableMemoryMailboxInterface()
1334 ControllerBaseAddress)) DAC960_V1_EnableMemoryMailboxInterface()
1339 CommandStatus = DAC960_PG_ReadStatusRegister(ControllerBaseAddress); DAC960_V1_EnableMemoryMailboxInterface()
1340 DAC960_PG_AcknowledgeHardwareMailboxInterrupt(ControllerBaseAddress); DAC960_V1_EnableMemoryMailboxInterface()
1341 DAC960_PG_AcknowledgeHardwareMailboxStatus(ControllerBaseAddress); DAC960_V1_EnableMemoryMailboxInterface()
1368 void __iomem *ControllerBaseAddress = Controller->BaseAddress; DAC960_V2_EnableMemoryMailboxInterface() local
1497 while (DAC960_GEM_HardwareMailboxFullP(ControllerBaseAddress)) DAC960_V2_EnableMemoryMailboxInterface()
1499 DAC960_GEM_WriteHardwareMailbox(ControllerBaseAddress, CommandMailboxDMA); DAC960_V2_EnableMemoryMailboxInterface()
1500 DAC960_GEM_HardwareMailboxNewCommand(ControllerBaseAddress); DAC960_V2_EnableMemoryMailboxInterface()
1501 while (!DAC960_GEM_HardwareMailboxStatusAvailableP(ControllerBaseAddress)) DAC960_V2_EnableMemoryMailboxInterface()
1503 CommandStatus = DAC960_GEM_ReadCommandStatus(ControllerBaseAddress); DAC960_V2_EnableMemoryMailboxInterface()
1504 DAC960_GEM_AcknowledgeHardwareMailboxInterrupt(ControllerBaseAddress); DAC960_V2_EnableMemoryMailboxInterface()
1505 DAC960_GEM_AcknowledgeHardwareMailboxStatus(ControllerBaseAddress); DAC960_V2_EnableMemoryMailboxInterface()
1508 while (DAC960_BA_HardwareMailboxFullP(ControllerBaseAddress)) DAC960_V2_EnableMemoryMailboxInterface()
1510 DAC960_BA_WriteHardwareMailbox(ControllerBaseAddress, CommandMailboxDMA); DAC960_V2_EnableMemoryMailboxInterface()
1511 DAC960_BA_HardwareMailboxNewCommand(ControllerBaseAddress); DAC960_V2_EnableMemoryMailboxInterface()
1512 while (!DAC960_BA_HardwareMailboxStatusAvailableP(ControllerBaseAddress)) DAC960_V2_EnableMemoryMailboxInterface()
1514 CommandStatus = DAC960_BA_ReadCommandStatus(ControllerBaseAddress); DAC960_V2_EnableMemoryMailboxInterface()
1515 DAC960_BA_AcknowledgeHardwareMailboxInterrupt(ControllerBaseAddress); DAC960_V2_EnableMemoryMailboxInterface()
1516 DAC960_BA_AcknowledgeHardwareMailboxStatus(ControllerBaseAddress); DAC960_V2_EnableMemoryMailboxInterface()
1519 while (DAC960_LP_HardwareMailboxFullP(ControllerBaseAddress)) DAC960_V2_EnableMemoryMailboxInterface()
1521 DAC960_LP_WriteHardwareMailbox(ControllerBaseAddress, CommandMailboxDMA); DAC960_V2_EnableMemoryMailboxInterface()
1522 DAC960_LP_HardwareMailboxNewCommand(ControllerBaseAddress); DAC960_V2_EnableMemoryMailboxInterface()
1523 while (!DAC960_LP_HardwareMailboxStatusAvailableP(ControllerBaseAddress)) DAC960_V2_EnableMemoryMailboxInterface()
1525 CommandStatus = DAC960_LP_ReadCommandStatus(ControllerBaseAddress); DAC960_V2_EnableMemoryMailboxInterface()
1526 DAC960_LP_AcknowledgeHardwareMailboxInterrupt(ControllerBaseAddress); DAC960_V2_EnableMemoryMailboxInterface()
1527 DAC960_LP_AcknowledgeHardwareMailboxStatus(ControllerBaseAddress); DAC960_V2_EnableMemoryMailboxInterface()
5267 void __iomem *ControllerBaseAddress = Controller->BaseAddress; DAC960_GEM_InterruptHandler() local
5272 DAC960_GEM_AcknowledgeInterrupt(ControllerBaseAddress); DAC960_GEM_InterruptHandler()
5308 void __iomem *ControllerBaseAddress = Controller->BaseAddress; DAC960_BA_InterruptHandler() local
5313 DAC960_BA_AcknowledgeInterrupt(ControllerBaseAddress); DAC960_BA_InterruptHandler()
5350 void __iomem *ControllerBaseAddress = Controller->BaseAddress; DAC960_LP_InterruptHandler() local
5355 DAC960_LP_AcknowledgeInterrupt(ControllerBaseAddress); DAC960_LP_InterruptHandler()
5392 void __iomem *ControllerBaseAddress = Controller->BaseAddress; DAC960_LA_InterruptHandler() local
5397 DAC960_LA_AcknowledgeInterrupt(ControllerBaseAddress); DAC960_LA_InterruptHandler()
5430 void __iomem *ControllerBaseAddress = Controller->BaseAddress; DAC960_PG_InterruptHandler() local
5435 DAC960_PG_AcknowledgeInterrupt(ControllerBaseAddress); DAC960_PG_InterruptHandler()
5468 void __iomem *ControllerBaseAddress = Controller->BaseAddress; DAC960_PD_InterruptHandler() local
5472 while (DAC960_PD_StatusAvailableP(ControllerBaseAddress)) DAC960_PD_InterruptHandler()
5475 DAC960_PD_ReadStatusCommandIdentifier(ControllerBaseAddress); DAC960_PD_InterruptHandler()
5478 DAC960_PD_ReadStatusRegister(ControllerBaseAddress); DAC960_PD_InterruptHandler()
5479 DAC960_PD_AcknowledgeInterrupt(ControllerBaseAddress); DAC960_PD_InterruptHandler()
5480 DAC960_PD_AcknowledgeStatus(ControllerBaseAddress); DAC960_PD_InterruptHandler()
5506 void __iomem *ControllerBaseAddress = Controller->BaseAddress; DAC960_P_InterruptHandler() local
5510 while (DAC960_PD_StatusAvailableP(ControllerBaseAddress)) DAC960_P_InterruptHandler()
5513 DAC960_PD_ReadStatusCommandIdentifier(ControllerBaseAddress); DAC960_P_InterruptHandler()
5519 DAC960_PD_ReadStatusRegister(ControllerBaseAddress); DAC960_P_InterruptHandler()
5520 DAC960_PD_AcknowledgeInterrupt(ControllerBaseAddress); DAC960_P_InterruptHandler()
5521 DAC960_PD_AcknowledgeStatus(ControllerBaseAddress); DAC960_P_InterruptHandler()

Completed in 190 milliseconds