| /linux-4.4.14/arch/blackfin/include/asm/ |
| H A D | blackfin.h | 34 /* CSYNC implementation for C file */ CSYNC()
35 static inline void CSYNC(void) CSYNC() function
59 /* SSYNC & CSYNC implementations for assembly files */
62 #define csync(x) CSYNC(x)
71 #define CSYNC(scratch) \ macro
74 CSYNC; \
79 #define CSYNC(scratch) CSYNC; macro
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| H A D | cplb.h | 114 /* CSYNC to ensure load store ordering */ _disable_cplb()
122 CSYNC(); disable_cplb()
134 /* CSYNC to ensure load store ordering */ _enable_cplb()
142 CSYNC(); enable_cplb()
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| H A D | entry.h | 135 CSYNC; \
164 CSYNC; \
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| H A D | ipipe.h | 165 CSYNC(); \
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| /linux-4.4.14/arch/blackfin/kernel/ |
| H A D | time-ts.c | 249 CSYNC(); bfin_coretmr_set_next_event()
251 CSYNC(); bfin_coretmr_set_next_event()
261 CSYNC(); bfin_coretmr_set_periodic()
265 CSYNC(); bfin_coretmr_set_periodic()
273 CSYNC(); bfin_coretmr_set_oneshot()
283 CSYNC(); bfin_coretmr_shutdown()
291 CSYNC(); bfin_coretmr_init()
298 CSYNC(); bfin_coretmr_init()
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| H A D | time.c | 54 CSYNC(); setup_core_timer()
64 CSYNC(); setup_core_timer()
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| H A D | kgdb.c | 317 CSYNC(); bfin_correct_hw_break()
320 CSYNC(); bfin_correct_hw_break()
329 CSYNC(); bfin_disable_hw_debug()
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| H A D | irqchip.c | 79 CSYNC(); maybe_lower_to_irq14()
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| H A D | early_printk.c | 190 CSYNC(); init_early_exception_vectors()
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| H A D | perf_event.c | 40 * 0x0C o CSYNC/SSYNC insn
54 * 0x0A s CSYNC/SSYNC stalls
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| H A D | traps.c | 59 CSYNC(); trap_init()
61 CSYNC(); trap_init()
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| H A D | trace.c | 294 pr_cont("CSYNC"); decode_ProgCtrl_0()
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| H A D | debug-mmrs.c | 106 DEFINE_SYSREG(syscfg, , CSYNC());
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| /linux-4.4.14/arch/blackfin/mach-bf561/ |
| H A D | coreb.c | 46 CSYNC(); coreb_ioctl()
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| H A D | atomic.S | 53 CSYNC(r2);
81 CSYNC(r2);
697 CSYNC(r2);
921 CSYNC(r2);
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| H A D | secondary.S | 62 CSYNC;
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| /linux-4.4.14/arch/blackfin/mach-common/ |
| H A D | cache-c.c | 49 CSYNC(); bfin_cache_init()
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| H A D | smp.c | 267 CSYNC(); setup_secondary()
269 CSYNC(); setup_secondary()
271 CSYNC(); setup_secondary()
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| H A D | ints-priority.c | 961 CSYNC(); init_exception_vectors()
1073 CSYNC(); init_arch_irq()
1075 CSYNC(); init_arch_irq()
1077 CSYNC(); init_arch_irq()
1193 CSYNC(); init_arch_irq()
1195 CSYNC(); init_arch_irq()
1197 CSYNC(); init_arch_irq()
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| H A D | head.S | 71 CSYNC;
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| H A D | pm.c | 125 CSYNC(); flushinv_all_dcache()
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| H A D | entry.S | 372 CSYNC; /* Disabling of CPLBs should be proceeded by a CSYNC */
380 CSYNC; /* Disabling of CPLBs should be proceeded by a CSYNC */
1199 CSYNC; /* Disabling of CPLBs should be proceeded by a CSYNC */
1207 CSYNC; /* Disabling of CPLBs should be proceeded by a CSYNC */
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| /linux-4.4.14/arch/blackfin/mach-bf609/ |
| H A D | dpm.S | 100 CSYNC;
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| /linux-4.4.14/arch/blackfin/mach-bf537/include/mach/ |
| H A D | anomaly.h | 48 /* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */
76 /* CSYNC/SSYNC/IDLE Causes Infinite Stall in Penultimate Instruction in Hardware Loop */
116 /* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
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| /linux-4.4.14/arch/blackfin/mach-bf538/include/mach/ |
| H A D | anomaly.h | 94 /* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
156 /* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */
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| /linux-4.4.14/arch/blackfin/mach-bf533/include/mach/ |
| H A D | anomaly.h | 108 /* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */
134 /* CSYNC/SSYNC/IDLE Causes Infinite Stall in Penultimate Instruction in Hardware Loop */
176 /* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
248 /* The IFLUSH Instruction Must Be Preceded by a CSYNC Instruction */
252 /* PREFETCH, FLUSH, and FLUSHINV Instructions Must Be Followed by a CSYNC Instruction */
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| /linux-4.4.14/arch/blackfin/mach-bf561/include/mach/ |
| H A D | anomaly.h | 116 /* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */
146 /* CSYNC/SSYNC/IDLE Causes Infinite Stall in Penultimate Instruction in Hardware Loop */
192 /* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
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| /linux-4.4.14/arch/blackfin/mach-bf548/include/mach/ |
| H A D | anomaly.h | 168 /* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
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| /linux-4.4.14/scripts/ |
| H A D | checkpatch.pl | 2940 ERROR("CSYNC",
2941 "use the CSYNC() macro in asm/blackfin.h\n" . $herevet);
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