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Searched refs:CP_PACKET3 (Results 1 – 8 of 8) sorted by relevance

/linux-4.4.14/drivers/gpu/drm/radeon/
Dr600_blit.c95 OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1)); in set_render_target()
98 OUT_RING(CP_PACKET3(R600_IT_SURFACE_BASE_UPDATE, 0)); in set_render_target()
102 OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1)); in set_render_target()
107 OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1)); in set_render_target()
111 OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1)); in set_render_target()
115 OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1)); in set_render_target()
119 OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1)); in set_render_target()
123 OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1)); in set_render_target()
127 OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1)); in set_render_target()
148 OUT_RING(CP_PACKET3(R600_IT_SURFACE_SYNC, 3)); in cp_set_surface_sync()
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Dradeon_state.c796 OUT_RING(CP_PACKET3(RADEON_CNTL_PAINT_MULTI, 4)); in radeon_clear_box()
939 OUT_RING(CP_PACKET3 in radeon_cp_dispatch_clear()
961 OUT_RING(CP_PACKET3 in radeon_cp_dispatch_clear()
1068 OUT_RING(CP_PACKET3 in radeon_cp_dispatch_clear()
1091 OUT_RING(CP_PACKET3 in radeon_cp_dispatch_clear()
1119 OUT_RING(CP_PACKET3 in radeon_cp_dispatch_clear()
1142 OUT_RING(CP_PACKET3(RADEON_3D_CLEAR_HIZ, 2)); in radeon_cp_dispatch_clear()
1259 OUT_RING(CP_PACKET3(R200_3D_DRAW_IMMD_2, 12)); in radeon_cp_dispatch_clear()
1331 OUT_RING(CP_PACKET3(RADEON_3D_DRAW_IMMD, 13)); in radeon_cp_dispatch_clear()
1563 OUT_RING(CP_PACKET3(RADEON_3D_RNDR_GEN_INDX_PRIM, 3)); in radeon_cp_dispatch_vertex()
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Dr300d.h40 #define CP_PACKET3 0xC0000000 macro
64 #define PACKET3(op, n) (CP_PACKET3 | \
Drv515d.h183 #define CP_PACKET3 0xC0000000 macro
204 #define PACKET3(op, n) (CP_PACKET3 | \
Dradeon_drv.h1922 #define CP_PACKET3( pkt, n ) \ macro
2040 OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1)); \
2046 OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1)); \
2052 OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1)); \
Dr300_cmdbuf.c448 OUT_RING(CP_PACKET3(R200_3D_DRAW_IMMD_2, 8)); in r300_emit_clear()
623 *cmd != CP_PACKET3(RADEON_CP_INDX_BUFFER, 2)) { in r300_emit_draw_indx_2()
Dr100d.h40 #define CP_PACKET3 0xC0000000 macro
63 #define PACKET3(op, n) (CP_PACKET3 | \
Dr600_cp.c2313 OUT_RING(CP_PACKET3(R600_IT_EVENT_WRITE, 0)); in r600_do_cp_idle()
2316 OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1)); in r600_do_cp_idle()
2335 OUT_RING(CP_PACKET3(R600_IT_ME_INITIALIZE, 5)); in r600_do_cp_start()
2407 OUT_RING(CP_PACKET3(R600_IT_INDIRECT_BUFFER, 2)); in r600_cp_dispatch_indirect()