Searched refs:CL (Results 1 - 58 of 58) sorted by relevance

/linux-4.4.14/drivers/gpu/drm/nouveau/nvkm/subdev/fb/
H A Dgddr3.c73 int CL, WR, CWL, DLL = 0, ODT = 0, RON, hi; nvkm_gddr3_calc() local
78 CL = ram->next->bios.timing_10_CL; nvkm_gddr3_calc()
86 CL = (ram->next->bios.timing[1] & 0x0000001f) >> 0; nvkm_gddr3_calc()
102 CL = ramxlat(hi ? ramgddr3_cl_hi : ramgddr3_cl_lo, CL); nvkm_gddr3_calc()
104 if (CL < 0 || CWL < 1 || CWL > 7 || WR < 0) nvkm_gddr3_calc()
109 ram->mr[0] |= (CL & 0x07) << 4; nvkm_gddr3_calc()
110 ram->mr[0] |= (CL & 0x08) >> 1; nvkm_gddr3_calc()
H A Dsddr3.c71 int CWL, CL, WR, DLL = 0, ODT = 0; nvkm_sddr3_calc() local
82 CL = ram->next->bios.timing_10_CL; nvkm_sddr3_calc()
88 CL = (ram->next->bios.timing[1] & 0x0000001f) >> 0; nvkm_sddr3_calc()
100 CL = ramxlat(ramddr3_cl, CL); nvkm_sddr3_calc()
102 if (CL < 0 || CWL < 0 || WR < 0) nvkm_sddr3_calc()
107 ram->mr[0] |= (CL & 0x0e) << 3; nvkm_sddr3_calc()
108 ram->mr[0] |= (CL & 0x01) << 2; nvkm_sddr3_calc()
H A Dsddr2.c62 int CL, WR, DLL = 0, ODT = 0; nvkm_sddr2_calc() local
66 CL = ram->next->bios.timing_10_CL; nvkm_sddr2_calc()
72 CL = (ram->next->bios.timing[1] & 0x0000001f); nvkm_sddr2_calc()
85 CL = ramxlat(ramddr2_cl, CL); nvkm_sddr2_calc()
87 if (CL < 0 || WR < 0) nvkm_sddr2_calc()
92 ram->mr[0] |= (CL & 0x07) << 4; nvkm_sddr2_calc()
H A Dgddr5.c38 int WL, CL, WR, at[2], dt, ds; nvkm_gddr5_calc() local
59 CL = (ram->next->bios.timing[1] & 0x0000001f); nvkm_gddr5_calc()
70 if (WL < 1 || WL > 7 || CL < 5 || CL > 36 || WR < 4 || WR > 35) nvkm_gddr5_calc()
72 CL -= 5; nvkm_gddr5_calc()
77 ram->mr[0] |= (CL & 0x0f) << 3; nvkm_gddr5_calc()
119 ram->mr[8] |= (CL & 0x10) >> 4; nvkm_gddr5_calc()
H A Dramnv50.c88 T(CWL) = T(CL) - 1; nv50_ram_timing_calc()
98 timing[6] = (0x2d + T(CL) - T(CWL) + nv50_ram_timing_calc()
101 (0x2f + T(CL) - T(CWL)); nv50_ram_timing_calc()
104 timing[6] = (0x2b + T(CL) - T(CWL)) << 16 | nv50_ram_timing_calc()
106 (0x2e + T(CL) - T(CWL)); nv50_ram_timing_calc()
113 (3 + T(CL) - T(CWL)); nv50_ram_timing_calc()
118 timing[3] = (unkt3b - 2 + T(CL)) << 24 | nv50_ram_timing_calc()
120 (T(CL) - 1) << 8 | nv50_ram_timing_calc()
121 (T(CL) - 1); nv50_ram_timing_calc()
129 timing[7] = (cur7 & 0xff00ffff) | (T(CL) - 1) << 16; nv50_ram_timing_calc()
134 timing[5] |= (T(CL) + 3) << 8; nv50_ram_timing_calc()
135 timing[8] |= (T(CL) - 4); nv50_ram_timing_calc()
138 timing[5] |= (T(CL) + 2) << 8; nv50_ram_timing_calc()
139 timing[8] |= (T(CL) - 2); nv50_ram_timing_calc()
163 T(CL) = (timing[3] & 0xff) + 1; nv50_ram_timing_read()
167 T(CWL) = T(CL) - 1; nv50_ram_timing_read()
H A Dramgt215.c364 T(CWL) = T(CL) - 1; gt215_ram_timing_calc()
378 (5 + T(CL) - T(CWL)); gt215_ram_timing_calc()
384 (0x30 + T(CL)) << 24 | gt215_ram_timing_calc()
385 (0xb + T(CL)) << 8 | gt215_ram_timing_calc()
386 (T(CL) - 1); gt215_ram_timing_calc()
393 max_t(u8, (T(CWL) + 6), (T(CL) + 2)) << 8 | gt215_ram_timing_calc()
395 timing[6] = (0x5a + T(CL)) << 16 | gt215_ram_timing_calc()
396 max_t(u8, 1, (6 - T(CL) + T(CWL))) << 8 | gt215_ram_timing_calc()
397 (0x50 + T(CL) - T(CWL)); gt215_ram_timing_calc()
399 ((tUNK_base + T(CL)) << 16) | gt215_ram_timing_calc()
408 timing[8] |= T(CL); gt215_ram_timing_calc()
/linux-4.4.14/include/video/
H A Dcirrus.h27 /* OLD COMMENT: for other CL-GD542x/543x based boards.. */
50 #define CL_SEQR14 0x14 /* Scratch Pad 2 (CL-GD5426/'28 Only) (do not access!) */
51 #define CL_SEQR15 0x15 /* Scratch Pad 3 (CL-GD5426/'28 Only) (do not access!) */
52 #define CL_SEQR16 0x16 /* Performance Tuning (CL-GD5424/'26/'28 Only) */
53 #define CL_SEQR17 0x17 /* Configuration ReadBack and Extended Control (CL-GF5428 Only) */
54 #define CL_SEQR18 0x18 /* Signature Generator Control (Not CL-GD5420) */
55 #define CL_SEQR19 0x19 /* Signature Generator Result Low Byte (Not CL-GD5420) */
56 #define CL_SEQR1A 0x1a /* Signature Generator Result High Byte (Not CL-GD5420) */
83 #define CL_GRC 0xc /* Color Key (CL-GD5424/'26/'28 Only) */
84 #define CL_GRD 0xd /* Color Key Mask (CL-GD5424/'26/'28 Only) */
87 #define CL_GR10 0x10 /* 16-bit Pixel BG Color High Byte (Not CL-GD5420) */
88 #define CL_GR11 0x11 /* 16-bit Pixel FG Color High Byte (Not CL-GD5420) */
93 /* the following are CL-GD5426/'28 specific blitter registers */
/linux-4.4.14/sound/soc/intel/skylake/
H A Dskl-sst-cldma.h47 /* CL: Software Position Based FIFO Capability Registers */
54 /* CL: Stream Descriptor x Control */
116 /* CL: Stream Descriptor x Status */
131 /* CL: Stream Descriptor x Last Valid Index */
136 /* CL: Stream Descriptor x FIFO Eviction Watermark */
142 /* CL: Stream Descriptor x Buffer Descriptor List Pointer Lower Base Address */
229 * @ops: operations supported on CL dma
H A Dskl-sst-cldma.c197 * The CL dma doesn't have any way to update the transfer status until a BDL
H A Dskl-sst.c96 dev_err(ctx->dev, "CL dma prepare failed : %d", ret); skl_load_base_firmware()
/linux-4.4.14/arch/powerpc/platforms/embedded6xx/
H A Dholly.c2 * Board setup routines for the IBM 750GX/CL platform w/ TSI10x bridge
133 printk(KERN_INFO "PPC750GX/CL Platform\n"); holly_setup_arch()
193 seq_printf(m, "machine\t\t: PPC750 GX/CL\n"); holly_show_cpuinfo()
275 .name = "PPC750 GX/CL TSI", define_machine()
/linux-4.4.14/fs/isofs/
H A Drock.h108 struct RR_CL_s CL; member in union:rock_ridge::__anon11586
H A Drock.c514 reloc_block = isonum_733(rr->u.CL.location); parse_rock_ridge_inode_internal()
/linux-4.4.14/arch/cris/arch-v32/mach-fs/
H A Ddram_init.S49 cmpq 2, $r1 ; CL = 2 ?
/linux-4.4.14/arch/arm/mach-clps711x/
H A Dboard-edb7211.c177 MACHINE_START(EDB7211, "CL-EDB7211 (EP7211 eval board)")
/linux-4.4.14/drivers/crypto/nx/
H A Dnx-842.h87 * "CRB Details - Normal Cop_Req (CL=00, C=1)"
/linux-4.4.14/arch/mips/pci/
H A Dfixup-sni.c41 * Logic CL-GD5434 VGA is device 3.
/linux-4.4.14/drivers/video/fbdev/
H A Dcirrusfb.c130 .name = "CL SD64",
147 .name = "CL Piccolo",
161 .name = "CL Picasso",
175 .name = "CL Spectrum",
189 .name = "CL Picasso4",
204 .name = "CL Alpine",
220 .name = "CL GD5480",
233 .name = "CL Laguna",
243 .name = "CL Laguna AGP",
267 CHIP(PCI_DEVICE_ID_CIRRUS_5462, BT_LAGUNA), /* CL Laguna */
268 CHIP(PCI_DEVICE_ID_CIRRUS_5464, BT_LAGUNA), /* CL Laguna 3D */
269 CHIP(PCI_DEVICE_ID_CIRRUS_5465, BT_LAGUNAB), /* CL Laguna 3DA*/
H A Duvesafb.c772 * hardware state data (CL = 0x0f). uvesafb_vbe_getstatesize()
H A Damifb.c316 Source: CL-GD542X Technical Reference Manual, Cirrus Logic, Oct 1992
/linux-4.4.14/drivers/misc/sgi-gru/
H A Dgrukservices.c128 union gru_mesqhead head __gru_cacheline_aligned__; /* CL 0 */
131 void *next __gru_cacheline_aligned__;/* CL 1 */
135 char data ____cacheline_aligned; /* CL 2 */
800 * bytes message size (<= 2 CL)
H A Dgrukservices.h47 int qlines; /* queue size in CL */
H A Dgrufault.c308 cbe->cbrexecstatus = 0; /* make CL dirty */ gru_flush_cache_cbe()
H A Dgrumain.c543 mb(); /* Let the CL flush complete */ gru_unload_context_data()
/linux-4.4.14/arch/mips/include/asm/emma/
H A Demma2rh.h209 #define CL 0x00000003 macro
/linux-4.4.14/arch/ia64/include/asm/sn/
H A Dtioca_provider.h182 * touch every CL aligned GART entry. tioca_tlbflush()
/linux-4.4.14/drivers/video/fbdev/aty/
H A Daty128fb.c314 u8 CL; member in struct:aty128_meminfo
329 .CL = 3,
343 .CL = 3,
357 .CL = 2,
371 .CL = 3,
1457 m->CL + aty128_ddafifo()
/linux-4.4.14/drivers/staging/comedi/drivers/
H A Damplc_dio200.c66 * Port CL - channels 16 to 19
H A Damplc_dio200_pci.c68 * Port CL - channels 16 to 19
H A Damplc_pci230.c166 * Port CL - channels 16 to 19
/linux-4.4.14/drivers/net/ieee802154/
H A Dat86rf230.c1426 * CL = 0.5 * (CX + CTRIM + CPAR) at86rf230_hw_init()
1429 * CL = capacitor of used crystal at86rf230_hw_init()
1440 * CL = 8 pF at86rf230_hw_init()
1451 * CL = 16 pF at86rf230_hw_init()
/linux-4.4.14/drivers/net/wireless/ath/
H A Dregd_common.h316 {CTRY_CHILE, APL6_WORLD, "CL"},
/linux-4.4.14/sound/soc/intel/common/
H A Dsst-dsp-priv.h311 /* To allocate CL dma buffers */
/linux-4.4.14/sound/pci/ice1712/
H A Dpsc724.c80 * CL (pin19) -- SCLK (VT1722 pin71)
H A Dse.c97 * CL (19pin) -- SCLK
/linux-4.4.14/drivers/pcmcia/
H A Di82365.c616 /* Check for Cirrus CL-PD67xx chips */ identify()
743 ISAPNP_FUNCTION(0x0e01), (unsigned long) "Cirrus Logic CL-PD6720" },
/linux-4.4.14/net/wireless/
H A Dchan.c722 /* only valid for GO and TDLS off-channel (station/p2p-CL) */ cfg80211_ir_permissive_chan()
/linux-4.4.14/drivers/tty/serial/
H A Ducc_uart.c125 u8 rx_length; /* 0x9C, Char length, set to 1+CL+PEN+1+SL */
864 u8 char_length = 2; /* 1 + CL + PEN + 1 + SL */ qe_uart_set_termios()
/linux-4.4.14/arch/powerpc/kernel/
H A Dcputable.c734 { /* 750CL (and "Broadway") */
737 .cpu_name = "750CL",
/linux-4.4.14/drivers/gpu/drm/i915/
H A Dintel_hdmi.c1750 * This a a bit weird since generally CL chv_hdmi_pre_pll_enable()
1752 * pick the CL based on the port. chv_hdmi_pre_pll_enable()
H A Dintel_dp.c2964 * This a a bit weird since generally CL chv_dp_pre_pll_enable()
2966 * pick the CL based on the port. chv_dp_pre_pll_enable()
/linux-4.4.14/drivers/isdn/hardware/eicon/
H A Dpc.h275 #define CL 0xb0 /* congestion level */ macro
/linux-4.4.14/drivers/net/wireless/ti/wlcore/
H A Ddebugfs.c469 wlvif->p2p ? "P2P-CL" : "STA"); wl12xx_for_each_wlvif_sta()
/linux-4.4.14/drivers/usb/storage/
H A Dtransport.c1096 usb_stor_dbg(us, "Bulk Command S 0x%x T 0x%x L %d F %d Trg %d LUN %d CL %d\n", usb_stor_Bulk_transport()
/linux-4.4.14/drivers/net/wireless/brcm80211/brcmfmac/
H A Dcfg80211.c5747 * #STA <= 1, #P2P-DEV <= 1, #{P2P-CL, P2P-GO} <= 1, channels = 1, 3 total
5748 * #STA <= 1, #P2P-DEV <= 1, #AP <= 1, #P2P-CL <= 1, channels = 1, 4 total
5753 * #STA <= 1, #P2P-DEV <= 1, #{P2P-CL, P2P-GO} <= 1, channels = 2, 3 total
5754 * #STA <= 1, #P2P-DEV <= 1, #AP <= 1, #P2P-CL <= 1, channels = 1, 4 total
/linux-4.4.14/drivers/clk/tegra/
H A Dclk-dfll.c20 * "CL-DVFS". To try to avoid confusion, this code refers to them
/linux-4.4.14/sound/pci/ac97/
H A Dac97_patch.c1236 /* OUTSEL */ 0xd794, /* CL:CL, SR:SR, LO:MX, LI:DS, MI:DS */ patch_sigmatel_stac9758()
1242 /* OUTSEL */ 0xfc70, /* CL:MX, SR:MX, LO:DS, LI:MX, MI:DS */ patch_sigmatel_stac9758()
/linux-4.4.14/drivers/memory/
H A Demif.c243 * Get the CL from SDRAM_CONFIG register
/linux-4.4.14/drivers/parisc/
H A Dlba_pci.c300 * clear error log bit (CL). \
/linux-4.4.14/net/decnet/
H A Daf_decnet.c2256 return " CL"; dn_state2asc()
/linux-4.4.14/arch/x86/kvm/
H A Demulate.c45 #define OpCL 9ull /* CL register (for shifts) */
379 /* 2 operand, src is CL */
/linux-4.4.14/include/sound/
H A Demu10k1.h115 /* or HLIPH. When IP is written with CL set, */
/linux-4.4.14/arch/blackfin/mach-bf518/include/mach/
H A DdefBF512.h1201 #define PWM_CHCL 0xffc03730 /* PWM Channel CL Duty Control (SR mode only) */
/linux-4.4.14/arch/tile/include/hv/
H A Dhypervisor.h1203 * interrupt, where CL is the client's PL. Upon entry to the INTCTRL_CL
/linux-4.4.14/net/mac80211/
H A Dmlme.c1801 sdata->wmm_acm |= BIT(4) | BIT(5); /* CL/VI */ ieee80211_sta_wmm_params()
/linux-4.4.14/drivers/gpu/drm/radeon/
H A Datombios.h6714 UCHAR ucNPL_RT; // Round trip delay (MC_SEQ_CAS_TIMING [28:24]:TCL=CL+NPL_RT-2). Always 2.
/linux-4.4.14/drivers/gpu/drm/amd/include/
H A Datombios.h7184 UCHAR ucNPL_RT; // Round trip delay (MC_SEQ_CAS_TIMING [28:24]:TCL=CL+NPL_RT-2). Always 2.
/linux-4.4.14/drivers/net/ethernet/broadcom/bnx2x/
H A Dbnx2x_reg.h1840 bits will be a '1' if that last command (#SET; #CL; or #FLOAT) for this

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