Searched refs:CDCLK_FREQ_SEL_MASK (Results 1 – 2 of 2) sorted by relevance
5687 val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK; in skl_dpll0_enable()6709 if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540) in skylake_get_display_clock_speed()6718 switch (cdctl & CDCLK_FREQ_SEL_MASK) { in skylake_get_display_clock_speed()6730 switch (cdctl & CDCLK_FREQ_SEL_MASK) { in skylake_get_display_clock_speed()
7395 #define CDCLK_FREQ_SEL_MASK (3<<26) macro