| H A D | clk-imx25.c | 36 #define CCM_CGCR1 0x10 macro
179 /* CCM_CGCR1(0): reserved in datasheet, used as audmux in FSL kernel */ __mx25_clocks_init()
180 clk[can1_ipg] = imx_clk_gate("can1_ipg", "ipg", ccm(CCM_CGCR1), 2); __mx25_clocks_init()
181 clk[can2_ipg] = imx_clk_gate("can2_ipg", "ipg", ccm(CCM_CGCR1), 3); __mx25_clocks_init()
182 clk[csi_ipg] = imx_clk_gate("csi_ipg", "ipg", ccm(CCM_CGCR1), 4); __mx25_clocks_init()
183 clk[cspi1_ipg] = imx_clk_gate("cspi1_ipg", "ipg", ccm(CCM_CGCR1), 5); __mx25_clocks_init()
184 clk[cspi2_ipg] = imx_clk_gate("cspi2_ipg", "ipg", ccm(CCM_CGCR1), 6); __mx25_clocks_init()
185 clk[cspi3_ipg] = imx_clk_gate("cspi3_ipg", "ipg", ccm(CCM_CGCR1), 7); __mx25_clocks_init()
186 clk[dryice_ipg] = imx_clk_gate("dryice_ipg", "ipg", ccm(CCM_CGCR1), 8); __mx25_clocks_init()
187 clk[ect_ipg] = imx_clk_gate("ect_ipg", "ipg", ccm(CCM_CGCR1), 9); __mx25_clocks_init()
188 clk[epit1_ipg] = imx_clk_gate("epit1_ipg", "ipg", ccm(CCM_CGCR1), 10); __mx25_clocks_init()
189 clk[epit2_ipg] = imx_clk_gate("epit2_ipg", "ipg", ccm(CCM_CGCR1), 11); __mx25_clocks_init()
190 /* CCM_CGCR1(12): reserved in datasheet, used as esai in FSL kernel */ __mx25_clocks_init()
191 clk[esdhc1_ipg] = imx_clk_gate("esdhc1_ipg", "ipg", ccm(CCM_CGCR1), 13); __mx25_clocks_init()
192 clk[esdhc2_ipg] = imx_clk_gate("esdhc2_ipg", "ipg", ccm(CCM_CGCR1), 14); __mx25_clocks_init()
193 clk[fec_ipg] = imx_clk_gate("fec_ipg", "ipg", ccm(CCM_CGCR1), 15); __mx25_clocks_init()
194 /* CCM_CGCR1(16): reserved in datasheet, used as gpio1 in FSL kernel */ __mx25_clocks_init()
195 /* CCM_CGCR1(17): reserved in datasheet, used as gpio2 in FSL kernel */ __mx25_clocks_init()
196 /* CCM_CGCR1(18): reserved in datasheet, used as gpio3 in FSL kernel */ __mx25_clocks_init()
197 clk[gpt1_ipg] = imx_clk_gate("gpt1_ipg", "ipg", ccm(CCM_CGCR1), 19); __mx25_clocks_init()
198 clk[gpt2_ipg] = imx_clk_gate("gpt2_ipg", "ipg", ccm(CCM_CGCR1), 20); __mx25_clocks_init()
199 clk[gpt3_ipg] = imx_clk_gate("gpt3_ipg", "ipg", ccm(CCM_CGCR1), 21); __mx25_clocks_init()
200 clk[gpt4_ipg] = imx_clk_gate("gpt4_ipg", "ipg", ccm(CCM_CGCR1), 22); __mx25_clocks_init()
201 /* CCM_CGCR1(23): reserved in datasheet, used as i2c1 in FSL kernel */ __mx25_clocks_init()
202 /* CCM_CGCR1(24): reserved in datasheet, used as i2c2 in FSL kernel */ __mx25_clocks_init()
203 /* CCM_CGCR1(25): reserved in datasheet, used as i2c3 in FSL kernel */ __mx25_clocks_init()
204 clk[iim_ipg] = imx_clk_gate("iim_ipg", "ipg", ccm(CCM_CGCR1), 26); __mx25_clocks_init()
205 /* CCM_CGCR1(27): reserved in datasheet, used as iomuxc in FSL kernel */ __mx25_clocks_init()
206 /* CCM_CGCR1(28): reserved in datasheet, used as kpp in FSL kernel */ __mx25_clocks_init()
207 clk[kpp_ipg] = imx_clk_gate("kpp_ipg", "ipg", ccm(CCM_CGCR1), 28); __mx25_clocks_init()
208 clk[lcdc_ipg] = imx_clk_gate("lcdc_ipg", "ipg", ccm(CCM_CGCR1), 29); __mx25_clocks_init()
209 /* CCM_CGCR1(30): reserved in datasheet, used as owire in FSL kernel */ __mx25_clocks_init()
210 clk[pwm1_ipg] = imx_clk_gate("pwm1_ipg", "ipg", ccm(CCM_CGCR1), 31); __mx25_clocks_init()
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