Searched refs:CACHELINESIZE (Results 1 - 5 of 5) sorted by relevance

/linux-4.4.14/arch/arm/mm/
H A Dproc-xscale.S42 #define CACHELINESIZE 32 define
95 add \rd, \rd, #CACHELINESIZE
97 add \rd, \rd, #CACHELINESIZE
99 add \rd, \rd, #CACHELINESIZE
101 add \rd, \rd, #CACHELINESIZE
242 add r0, r0, #CACHELINESIZE
264 bic r0, r0, #CACHELINESIZE - 1
266 add r0, r0, #CACHELINESIZE
285 bic r0, r0, #CACHELINESIZE - 1
288 add r0, r0, #CACHELINESIZE
309 add r0, r0, #CACHELINESIZE
329 tst r0, #CACHELINESIZE - 1
330 bic r0, r0, #CACHELINESIZE - 1
332 tst r1, #CACHELINESIZE - 1
335 add r0, r0, #CACHELINESIZE
350 bic r0, r0, #CACHELINESIZE - 1
352 add r0, r0, #CACHELINESIZE
367 bic r0, r0, #CACHELINESIZE - 1
370 add r0, r0, #CACHELINESIZE
458 add r0, r0, #CACHELINESIZE
459 subs r1, r1, #CACHELINESIZE
H A Dproc-xsc3.S46 #define CACHELINESIZE 32 define
201 add r0, r0, #CACHELINESIZE
226 bic r0, r0, #CACHELINESIZE - 1
228 add r0, r0, #CACHELINESIZE
249 add r0, r0, #CACHELINESIZE
270 tst r0, #CACHELINESIZE - 1
271 bic r0, r0, #CACHELINESIZE - 1
273 tst r1, #CACHELINESIZE - 1
276 add r0, r0, #CACHELINESIZE
291 bic r0, r0, #CACHELINESIZE - 1
293 add r0, r0, #CACHELINESIZE
308 bic r0, r0, #CACHELINESIZE - 1
310 add r0, r0, #CACHELINESIZE
348 add r0, r0, #CACHELINESIZE
349 subs r1, r1, #CACHELINESIZE
/linux-4.4.14/drivers/mtd/maps/
H A Dpxa2xx-flash.c26 #define CACHELINESIZE 32 macro
34 start &= ~(CACHELINESIZE - 1); pxa2xx_map_inval_cache()
38 start += CACHELINESIZE; pxa2xx_map_inval_cache()
/linux-4.4.14/drivers/ide/
H A Dcs5530.c175 * --> Write 0x04 into 8-bit PCI CACHELINESIZE reg of function 0 of the cs5530 init_chipset_cs5530()
/linux-4.4.14/drivers/ata/
H A Dpata_cs5530.c233 * --> Write 0x04 into 8-bit PCI CACHELINESIZE reg of function 0 of the cs5530 cs5530_init_chip()

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