Searched refs:BANK_HEIGHT (Results 1 – 10 of 10) sorted by relevance
65 #define BANK_HEIGHT(x) ((x) << GB_MACROTILE_MODE0__BANK_HEIGHT__SHIFT) macro1518 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | in gfx_v8_0_tiling_mode_table_init()1524 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | in gfx_v8_0_tiling_mode_table_init()1530 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | in gfx_v8_0_tiling_mode_table_init()1536 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | in gfx_v8_0_tiling_mode_table_init()1542 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | in gfx_v8_0_tiling_mode_table_init()1548 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | in gfx_v8_0_tiling_mode_table_init()1554 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | in gfx_v8_0_tiling_mode_table_init()1560 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) | in gfx_v8_0_tiling_mode_table_init()1566 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | in gfx_v8_0_tiling_mode_table_init()[all …]
1206 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | in gfx_v7_0_tiling_mode_table_init()1212 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | in gfx_v7_0_tiling_mode_table_init()1218 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | in gfx_v7_0_tiling_mode_table_init()1224 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | in gfx_v7_0_tiling_mode_table_init()1230 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | in gfx_v7_0_tiling_mode_table_init()1236 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | in gfx_v7_0_tiling_mode_table_init()1242 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | in gfx_v7_0_tiling_mode_table_init()1248 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) | in gfx_v7_0_tiling_mode_table_init()1254 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | in gfx_v7_0_tiling_mode_table_init()1260 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | in gfx_v7_0_tiling_mode_table_init()[all …]
192 # define BANK_HEIGHT(x) ((x) << 2) macro
2108 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); in dce_v8_0_crtc_do_set_base()
2166 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); in dce_v11_0_crtc_do_set_base()
2178 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); in dce_v10_0_crtc_do_set_base()
2472 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | in si_tiling_mode_table_init()2482 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | in si_tiling_mode_table_init()2492 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | in si_tiling_mode_table_init()2502 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | in si_tiling_mode_table_init()2512 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | in si_tiling_mode_table_init()2522 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | in si_tiling_mode_table_init()2532 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | in si_tiling_mode_table_init()2542 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | in si_tiling_mode_table_init()2552 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | in si_tiling_mode_table_init()2562 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | in si_tiling_mode_table_init()[all …]
2504 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | in cik_tiling_mode_table_init()2510 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | in cik_tiling_mode_table_init()2516 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | in cik_tiling_mode_table_init()2522 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | in cik_tiling_mode_table_init()2528 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | in cik_tiling_mode_table_init()2534 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | in cik_tiling_mode_table_init()2540 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | in cik_tiling_mode_table_init()2546 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | in cik_tiling_mode_table_init()2552 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | in cik_tiling_mode_table_init()2558 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | in cik_tiling_mode_table_init()[all …]
1210 # define BANK_HEIGHT(x) ((x) << 16) macro
1267 # define BANK_HEIGHT(x) ((x) << 2) macro