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Searched refs:ATH25_REG_MS (Results 1 – 3 of 3) sorted by relevance

/linux-4.4.14/arch/mips/ath25/
Dar2315.c213 refdiv = ATH25_REG_MS(pllc_ctrl, AR2315_PLLC_REF_DIV); in ar2315_sys_clk()
215 fdiv = ATH25_REG_MS(pllc_ctrl, AR2315_PLLC_FDBACK_DIV); in ar2315_sys_clk()
216 divby2 = ATH25_REG_MS(pllc_ctrl, AR2315_PLLC_ADD_FDBACK_DIV) + 1; in ar2315_sys_clk()
223 clk_div = ATH25_REG_MS(pllc_ctrl, AR2315_PLLC_CLKM_DIV); in ar2315_sys_clk()
227 clk_div = ATH25_REG_MS(pllc_ctrl, AR2315_PLLC_CLKC_DIV); in ar2315_sys_clk()
236 cpu_div = ATH25_REG_MS(clock_ctl, AR2315_CPUCLK_CLK_DIV); in ar2315_sys_clk()
268 memsize = 1 + ATH25_REG_MS(memcfg, AR2315_MEM_CFG_DATA_WIDTH); in ar2315_plat_mem_setup()
269 memsize <<= 1 + ATH25_REG_MS(memcfg, AR2315_MEM_CFG_COL_WIDTH); in ar2315_plat_mem_setup()
270 memsize <<= 1 + ATH25_REG_MS(memcfg, AR2315_MEM_CFG_ROW_WIDTH); in ar2315_plat_mem_setup()
Ddevices.h6 #define ATH25_REG_MS(_val, _field) (((_val) & _field##_M) >> _field##_S) macro
Dar5312.c364 bank0_ac = ATH25_REG_MS(memcfg, AR5312_MEM_CFG1_AC0); in ar5312_plat_mem_setup()
365 bank1_ac = ATH25_REG_MS(memcfg, AR5312_MEM_CFG1_AC1); in ar5312_plat_mem_setup()