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Searched refs:AR_SM_BASE (Results 1 - 2 of 2) sorted by relevance

/linux-4.4.14/drivers/net/wireless/ath/ath9k/
H A D	ar9003_phy.h	451 #define AR_SM_BASE 0xa200 macro 453 #define AR_PHY_D2_CHIP_ID (AR_SM_BASE + 0x0) 454 #define AR_PHY_GEN_CTRL (AR_SM_BASE + 0x4) 455 #define AR_PHY_MODE (AR_SM_BASE + 0x8) 456 #define AR_PHY_ACTIVE (AR_SM_BASE + 0xc) 457 #define AR_PHY_SPUR_MASK_A (AR_SM_BASE + (AR_SREV_9561(ah) ? 0x18 : 0x20)) 458 #define AR_PHY_SPUR_MASK_B (AR_SM_BASE + (AR_SREV_9561(ah) ? 0x1c : 0x24)) 459 #define AR_PHY_SPECTRAL_SCAN (AR_SM_BASE + 0x28) 460 #define AR_PHY_RADAR_BW_FILTER (AR_SM_BASE + 0x2c) 461 #define AR_PHY_SEARCH_START_DELAY (AR_SM_BASE + 0x30) 462 #define AR_PHY_MAX_RX_LEN (AR_SM_BASE + 0x34) 463 #define AR_PHY_FRAME_CTL (AR_SM_BASE + 0x38) 464 #define AR_PHY_RFBUS_REQ (AR_SM_BASE + 0x3c) 465 #define AR_PHY_RFBUS_GRANT (AR_SM_BASE + 0x40) 466 #define AR_PHY_RIFS (AR_SM_BASE + 0x44) 467 #define AR_PHY_RX_CLR_DELAY (AR_SM_BASE + 0x50) 468 #define AR_PHY_RX_DELAY (AR_SM_BASE + 0x54) 470 #define AR_PHY_XPA_TIMING_CTL (AR_SM_BASE + 0x64) 471 #define AR_PHY_MISC_PA_CTL (AR_SM_BASE + 0x80) 472 #define AR_PHY_SWITCH_CHAIN_0 (AR_SM_BASE + 0x84) 473 #define AR_PHY_SWITCH_COM (AR_SM_BASE + 0x88) 474 #define AR_PHY_SWITCH_COM_2 (AR_SM_BASE + 0x8c) 475 #define AR_PHY_RX_CHAINMASK (AR_SM_BASE + 0xa0) 476 #define AR_PHY_CAL_CHAINMASK (AR_SM_BASE + 0xc0) 477 #define AR_PHY_CALMODE (AR_SM_BASE + 0xc8) 478 #define AR_PHY_FCAL_1 (AR_SM_BASE + 0xcc) 479 #define AR_PHY_FCAL_2_0 (AR_SM_BASE + 0xd0) 480 #define AR_PHY_DFT_TONE_CTL_0 (AR_SM_BASE + 0xd4) 481 #define AR_PHY_CL_CAL_CTL (AR_SM_BASE + 0xd8) 482 #define AR_PHY_CL_TAB_0 (AR_SM_BASE + 0x100) 483 #define AR_PHY_SYNTH_CONTROL (AR_SM_BASE + 0x140) 484 #define AR_PHY_ADDAC_CLK_SEL (AR_SM_BASE + 0x144) 485 #define AR_PHY_PLL_CTL (AR_SM_BASE + 0x148) 486 #define AR_PHY_ANALOG_SWAP (AR_SM_BASE + 0x14c) 487 #define AR_PHY_ADDAC_PARA_CTL (AR_SM_BASE + 0x150) 488 #define AR_PHY_XPA_CFG (AR_SM_BASE + 0x158) 498 #define AR_PHY_TEST (AR_SM_BASE + (AR_SREV_9561(ah) ? 0x15c : 0x160)) 509 #define AR_PHY_TEST_CTL_STATUS (AR_SM_BASE + (AR_SREV_9561(ah) ? 0x160 : 0x164)) 524 #define AR_PHY_TSTDAC (AR_SM_BASE + (AR_SREV_9561(ah) ? 0x164 : 0x168)) 526 #define AR_PHY_CHAN_STATUS (AR_SM_BASE + (AR_SREV_9561(ah) ? 0x168 : 0x16c)) 528 #define AR_PHY_CHAN_INFO_MEMORY (AR_SM_BASE + (AR_SREV_9561(ah) ? 0x16c : 0x170)) 532 #define AR_PHY_CHNINFO_NOISEPWR (AR_SM_BASE + (AR_SREV_9561(ah) ? 0x170 : 0x174)) 533 #define AR_PHY_CHNINFO_GAINDIFF (AR_SM_BASE + (AR_SREV_9561(ah) ? 0x174 : 0x178)) 534 #define AR_PHY_CHNINFO_FINETIM (AR_SM_BASE + (AR_SREV_9561(ah) ? 0x178 : 0x17c)) 535 #define AR_PHY_CHAN_INFO_GAIN_0 (AR_SM_BASE + (AR_SREV_9561(ah) ? 0x17c : 0x180)) 536 #define AR_PHY_SCRAMBLER_SEED (AR_SM_BASE + (AR_SREV_9561(ah) ? 0x184 : 0x190)) 537 #define AR_PHY_CCK_TX_CTRL (AR_SM_BASE + (AR_SREV_9561(ah) ? 0x188 : 0x194)) 539 #define AR_PHY_HEAVYCLIP_CTL (AR_SM_BASE + (AR_SREV_9561(ah) ? 0x198 : 0x1a4)) 540 #define AR_PHY_HEAVYCLIP_20 (AR_SM_BASE + 0x1a8) 541 #define AR_PHY_HEAVYCLIP_40 (AR_SM_BASE + 0x1ac) 542 #define AR_PHY_HEAVYCLIP_1 (AR_SM_BASE + 0x19c) 543 #define AR_PHY_HEAVYCLIP_2 (AR_SM_BASE + 0x1a0) 544 #define AR_PHY_HEAVYCLIP_3 (AR_SM_BASE + 0x1a4) 545 #define AR_PHY_HEAVYCLIP_4 (AR_SM_BASE + 0x1a8) 546 #define AR_PHY_HEAVYCLIP_5 (AR_SM_BASE + 0x1ac) 547 #define AR_PHY_ILLEGAL_TXRATE (AR_SM_BASE + 0x1b0) 549 #define AR_PHY_POWER_TX_RATE(_d) (AR_SM_BASE + 0x1c0 + ((_d) << 2)) 551 #define AR_PHY_PWRTX_MAX (AR_SM_BASE + 0x1f0) 552 #define AR_PHY_POWER_TX_SUB (AR_SM_BASE + 0x1f4) 554 #define AR_PHY_TPC_1 (AR_SM_BASE + 0x1f8) 560 #define AR_PHY_TPC_4_B0 (AR_SM_BASE + 0x204) 561 #define AR_PHY_TPC_5_B0 (AR_SM_BASE + 0x208) 562 #define AR_PHY_TPC_6_B0 (AR_SM_BASE + 0x20c) 564 #define AR_PHY_TPC_11_B0 (AR_SM_BASE + 0x220) 570 #define AR_PHY_TPC_12 (AR_SM_BASE + 0x224) 574 #define AR_PHY_TPC_18 (AR_SM_BASE + 0x23c) 580 #define AR_PHY_TPC_19 (AR_SM_BASE + 0x240) 586 #define AR_PHY_TX_FORCED_GAIN (AR_SM_BASE + 0x258) 607 #define AR_PHY_PDADC_TAB_0 (AR_SM_BASE + 0x280) 609 #define AR_PHY_TXGAIN_TABLE (AR_SM_BASE + 0x300) 611 #define AR_PHY_TX_IQCAL_CONTROL_0 (AR_SM_BASE + (AR_SREV_9485(ah) ? \ 613 #define AR_PHY_TX_IQCAL_CONTROL_1 (AR_SM_BASE + (AR_SREV_9485(ah) ? \ 615 #define AR_PHY_TX_IQCAL_START (AR_SM_BASE + (AR_SREV_9485(ah) ? \ 617 #define AR_PHY_TX_IQCAL_STATUS_B0 (AR_SM_BASE + (AR_SREV_9485(ah) ? \ 619 #define AR_PHY_TX_IQCAL_CORR_COEFF_B0(_i) (AR_SM_BASE + \ 622 #define AR_PHY_RTT_CTRL (AR_SM_BASE + 0x380) 624 #define AR_PHY_WATCHDOG_STATUS (AR_SM_BASE + 0x5c0) 625 #define AR_PHY_WATCHDOG_CTL_1 (AR_SM_BASE + 0x5c4) 626 #define AR_PHY_WATCHDOG_CTL_2 (AR_SM_BASE + 0x5c8) 627 #define AR_PHY_WATCHDOG_CTL (AR_SM_BASE + 0x5cc) 628 #define AR_PHY_ONLY_WARMRESET (AR_SM_BASE + 0x5d0) 629 #define AR_PHY_ONLY_CTL (AR_SM_BASE + 0x5d4) 630 #define AR_PHY_ECO_CTRL (AR_SM_BASE + 0x5dc) 632 #define AR_PHY_BB_THERM_ADC_1 (AR_SM_BASE + 0x248) 636 #define AR_PHY_BB_THERM_ADC_3 (AR_SM_BASE + 0x250) 642 #define AR_PHY_BB_THERM_ADC_4 (AR_SM_BASE + 0x254) 988 AR_SM1_BASE : AR_SM_BASE)) 990 AR_SM1_BASE : AR_SM_BASE)) 1117 #define AR_PHY_XPA_TIMING_CTL (AR_SM_BASE + 0x64) 1157 #define AR_PHY_PAPRD_TRAINER_CNTL1 (AR_SM_BASE + (AR_SREV_9485(ah) ? 0x580 : 0x490)) 1174 #define AR_PHY_PAPRD_TRAINER_CNTL2 (AR_SM_BASE + (AR_SREV_9485(ah) ? 0x584 : 0x494)) 1179 #define AR_PHY_PAPRD_TRAINER_CNTL3 (AR_SM_BASE + (AR_SREV_9485(ah) ? 0x588 : 0x498)) 1196 #define AR_PHY_PAPRD_TRAINER_CNTL4 (AR_SM_BASE + (AR_SREV_9485(ah) ? 0x58c : 0x49c)) 1216 #define AR_PHY_PAPRD_TRAINER_STAT1 (AR_SM_BASE + (AR_SREV_9485(ah) ? 0x590 : 0x4a0)) 1231 #define AR_PHY_PAPRD_TRAINER_STAT2 (AR_SM_BASE + (AR_SREV_9485(ah) ? 0x594 : 0x4a4)) 1240 #define AR_PHY_PAPRD_TRAINER_STAT3 (AR_SM_BASE + (AR_SREV_9485(ah) ? 0x598 : 0x4a8)) 1255 #define AR_PHY_POWERTX_RATE5 (AR_SM_BASE + 0x1d0) 1259 #define AR_PHY_POWERTX_RATE6 (AR_SM_BASE + 0x1d4) 1263 #define AR_PHY_POWERTX_RATE8 (AR_SM_BASE + 0x1dc)
H A D	reg_aic.h	20 #define AR_SM_BASE 0xa200 macro 24 #define AR_PHY_AIC_CTRL_0_B0 (AR_SM_BASE + 0x4b0) 25 #define AR_PHY_AIC_CTRL_1_B0 (AR_SM_BASE + 0x4b4) 26 #define AR_PHY_AIC_CTRL_2_B0 (AR_SM_BASE + 0x4b8) 27 #define AR_PHY_AIC_CTRL_3_B0 (AR_SM_BASE + 0x4bc) 28 #define AR_PHY_AIC_CTRL_4_B0 (AR_SM_BASE + 0x4c0) 30 #define AR_PHY_AIC_STAT_0_B0 (AR_SM_BASE + 0x4c4) 31 #define AR_PHY_AIC_STAT_1_B0 (AR_SM_BASE + 0x4c8) 32 #define AR_PHY_AIC_STAT_2_B0 (AR_SM_BASE + 0x4cc) 42 #define AR_PHY_AIC_SRAM_ADDR_B0 (AR_SM_BASE + 0x5f0) 43 #define AR_PHY_AIC_SRAM_DATA_B0 (AR_SM_BASE + 0x5f4)

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