Searched refs:ver_sync_start (Results 1 – 3 of 3) sorted by relevance
47 raw.ver_sync_start = timing->ver_sync_start - 1; in via_set_primary_timing()63 | (raw.ver_sync_start >> (8 - 2) & 0x04) in via_set_primary_timing()67 | (raw.ver_sync_start >> (9 - 7) & 0x80), 0xEF); in via_set_primary_timing()70 via_write_reg(VIACR, 0x10, raw.ver_sync_start & 0xFF); in via_set_primary_timing()78 | (raw.ver_sync_start >> (10 - 1) & 0x02) in via_set_primary_timing()105 raw.ver_sync_start = timing->ver_sync_start - 1; in via_set_secondary_timing()131 via_write_reg(VIACR, 0x5E, raw.ver_sync_start & 0xFF); in via_set_secondary_timing()133 | (raw.ver_sync_start >> (8 - 5) & 0xE0)); in via_set_secondary_timing()
47 u16 ver_sync_start; member
1483 timing.ver_sync_start = timing.ver_addr + var->lower_margin + dy; in var_to_timing()1484 timing.ver_sync_end = timing.ver_sync_start + var->vsync_len; in var_to_timing()