| /linux-4.1.27/drivers/gpu/drm/radeon/ |
| H A D | btc_dpm.c | 1310 u16 *vddc, u16 *vddci) btc_apply_voltage_delta_rules()
1315 if ((0 == *vddc) || (0 == *vddci)) btc_apply_voltage_delta_rules()
1318 if (*vddc > *vddci) { btc_apply_voltage_delta_rules()
1319 if ((*vddc - *vddci) > rdev->pm.dpm.dyn_state.vddc_vddci_delta) { btc_apply_voltage_delta_rules()
1322 *vddci = (new_voltage < max_vddci) ? new_voltage : max_vddci; btc_apply_voltage_delta_rules()
1325 if ((*vddci - *vddc) > rdev->pm.dpm.dyn_state.vddc_vddci_delta) { btc_apply_voltage_delta_rules()
1327 (*vddci - rdev->pm.dpm.dyn_state.vddc_vddci_delta)); btc_apply_voltage_delta_rules()
1801 if (state->low.vddci != ulv_pl->vddci) btc_is_state_ulv_compatible()
2102 u16 vddc, vddci; btc_apply_state_adjust_rules() local
2122 if (ps->high.vddci > max_limits->vddci) btc_apply_state_adjust_rules()
2123 ps->high.vddci = max_limits->vddci; btc_apply_state_adjust_rules()
2131 if (ps->medium.vddci > max_limits->vddci) btc_apply_state_adjust_rules()
2132 ps->medium.vddci = max_limits->vddci; btc_apply_state_adjust_rules()
2140 if (ps->low.vddci > max_limits->vddci) btc_apply_state_adjust_rules()
2141 ps->low.vddci = max_limits->vddci; btc_apply_state_adjust_rules()
2150 vddci = ps->high.vddci; btc_apply_state_adjust_rules()
2155 vddci = ps->low.vddci; btc_apply_state_adjust_rules()
2162 ps->low.vddci = vddci; btc_apply_state_adjust_rules()
2184 ps->low.vddci = vddci; btc_apply_state_adjust_rules()
2186 ps->medium.vddci = vddci; btc_apply_state_adjust_rules()
2188 ps->high.vddci = vddci; btc_apply_state_adjust_rules()
2192 if (ps->medium.vddci < ps->low.vddci) btc_apply_state_adjust_rules()
2193 ps->medium.vddci = ps->low.vddci; btc_apply_state_adjust_rules()
2196 if (ps->high.vddci < ps->medium.vddci) btc_apply_state_adjust_rules()
2197 ps->high.vddci = ps->medium.vddci; btc_apply_state_adjust_rules()
2212 ps->low.mclk, max_limits->vddci, &ps->low.vddci); btc_apply_state_adjust_rules()
2221 ps->medium.mclk, max_limits->vddci, &ps->medium.vddci); btc_apply_state_adjust_rules()
2230 ps->high.mclk, max_limits->vddci, &ps->high.vddci); btc_apply_state_adjust_rules()
2236 btc_apply_voltage_delta_rules(rdev, max_limits->vddc, max_limits->vddci, btc_apply_state_adjust_rules()
2237 &ps->low.vddc, &ps->low.vddci); btc_apply_state_adjust_rules()
2238 btc_apply_voltage_delta_rules(rdev, max_limits->vddc, max_limits->vddci, btc_apply_state_adjust_rules()
2239 &ps->medium.vddc, &ps->medium.vddci); btc_apply_state_adjust_rules()
2240 btc_apply_voltage_delta_rules(rdev, max_limits->vddc, max_limits->vddci, btc_apply_state_adjust_rules()
2241 &ps->high.vddc, &ps->high.vddci); btc_apply_state_adjust_rules()
2754 seq_printf(m, "power level %d sclk: %u mclk: %u vddc: %u vddci: %u\n", btc_dpm_debugfs_print_current_performance_level()
2755 current_index, pl->sclk, pl->mclk, pl->vddc, pl->vddci); btc_dpm_debugfs_print_current_performance_level()
1308 btc_apply_voltage_delta_rules(struct radeon_device *rdev, u16 max_vddc, u16 max_vddci, u16 *vddc, u16 *vddci) btc_apply_voltage_delta_rules() argument
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| H A D | btc_dpm.h | 53 u16 *vddc, u16 *vddci);
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| H A D | ni_dpm.c | 792 u16 vddci; ni_apply_state_adjust_rules() local
814 if (ps->performance_levels[i].vddci > max_limits->vddci) ni_apply_state_adjust_rules()
815 ps->performance_levels[i].vddci = max_limits->vddci; ni_apply_state_adjust_rules()
825 ps->performance_levels[0].vddci = ni_apply_state_adjust_rules()
826 ps->performance_levels[ps->performance_level_count - 1].vddci; ni_apply_state_adjust_rules()
843 vddci = ps->performance_levels[0].vddci; ni_apply_state_adjust_rules()
847 if (vddci < ps->performance_levels[i].vddci) ni_apply_state_adjust_rules()
848 vddci = ps->performance_levels[i].vddci; ni_apply_state_adjust_rules()
852 ps->performance_levels[i].vddci = vddci; ni_apply_state_adjust_rules()
858 if (ps->performance_levels[i].vddci < ps->performance_levels[i - 1].vddci) ni_apply_state_adjust_rules()
859 ps->performance_levels[i].vddci = ps->performance_levels[i - 1].vddci; ni_apply_state_adjust_rules()
878 max_limits->vddci, &ps->performance_levels[i].vddci); ni_apply_state_adjust_rules()
889 max_limits->vddc, max_limits->vddci, ni_apply_state_adjust_rules()
891 &ps->performance_levels[i].vddci); ni_apply_state_adjust_rules()
1748 initial_state->performance_levels[0].vddci, ni_populate_smc_initial_state()
1749 &table->initialState.levels[0].vddci); ni_populate_smc_initial_state()
1862 &table->ACPIState.levels[0].vddci); ni_populate_smc_acpi_state()
2380 pl->vddci, &level->vddci); ni_convert_power_level_to_smc()
3937 pl->vddci = le16_to_cpu(clock_info->evergreen.usVDDCI); ni_parse_pplib_clock_info()
3948 eg_pi->acpi_vddci = pl->vddci; ni_parse_pplib_clock_info()
3968 u16 vddc, vddci, mvdd; ni_parse_pplib_clock_info() local
3969 radeon_atombios_get_default_voltages(rdev, &vddc, &vddci, &mvdd); ni_parse_pplib_clock_info()
3973 pl->vddci = vddci; ni_parse_pplib_clock_info()
3981 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = pl->vddci; ni_parse_pplib_clock_info()
4292 printk("\t\tpower level %d sclk: %u mclk: %u vddc: %u vddci: %u pcie gen: %u\n", ni_dpm_print_power_state()
4293 i, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1); ni_dpm_print_power_state()
4295 printk("\t\tpower level %d sclk: %u mclk: %u vddc: %u vddci: %u\n", ni_dpm_print_power_state()
4296 i, pl->sclk, pl->mclk, pl->vddc, pl->vddci); ni_dpm_print_power_state()
4317 seq_printf(m, "power level %d sclk: %u mclk: %u vddc: %u vddci: %u\n", ni_dpm_debugfs_print_current_performance_level()
4318 current_index, pl->sclk, pl->mclk, pl->vddc, pl->vddci); ni_dpm_debugfs_print_current_performance_level()
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| H A D | rv770_dpm.c | 2204 pl->vddci = le16_to_cpu(clock_info->evergreen.usVDDCI); rv7xx_parse_pplib_clock_info()
2228 eg_pi->acpi_vddci = pl->vddci; rv7xx_parse_pplib_clock_info()
2250 u16 vddc, vddci, mvdd; rv7xx_parse_pplib_clock_info() local
2251 radeon_atombios_get_default_voltages(rdev, &vddc, &vddci, &mvdd); rv7xx_parse_pplib_clock_info()
2255 pl->vddci = vddci; rv7xx_parse_pplib_clock_info()
2263 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = pl->vddci; rv7xx_parse_pplib_clock_info()
2443 printk("\t\tpower level 0 sclk: %u mclk: %u vddc: %u vddci: %u\n", rv770_dpm_print_power_state()
2444 pl->sclk, pl->mclk, pl->vddc, pl->vddci); rv770_dpm_print_power_state()
2446 printk("\t\tpower level 1 sclk: %u mclk: %u vddc: %u vddci: %u\n", rv770_dpm_print_power_state()
2447 pl->sclk, pl->mclk, pl->vddc, pl->vddci); rv770_dpm_print_power_state()
2449 printk("\t\tpower level 2 sclk: %u mclk: %u vddc: %u vddci: %u\n", rv770_dpm_print_power_state()
2450 pl->sclk, pl->mclk, pl->vddc, pl->vddci); rv770_dpm_print_power_state()
2486 seq_printf(m, "power level %d sclk: %u mclk: %u vddc: %u vddci: %u\n", rv770_dpm_debugfs_print_current_performance_level()
2487 current_index, pl->sclk, pl->mclk, pl->vddc, pl->vddci); rv770_dpm_debugfs_print_current_performance_level()
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| H A D | si_dpm.c | 2944 u16 vddc, vddci; si_apply_state_adjust_rules() local
2989 if (ps->performance_levels[i].vddci > max_limits->vddci) si_apply_state_adjust_rules()
2990 ps->performance_levels[i].vddci = max_limits->vddci; si_apply_state_adjust_rules()
3029 vddci = ps->performance_levels[ps->performance_level_count - 1].vddci; si_apply_state_adjust_rules()
3032 vddci = ps->performance_levels[0].vddci; si_apply_state_adjust_rules()
3047 ps->performance_levels[0].vddci = vddci; si_apply_state_adjust_rules()
3076 ps->performance_levels[i].vddci = vddci; si_apply_state_adjust_rules()
3082 if (ps->performance_levels[i].vddci < ps->performance_levels[i - 1].vddci) si_apply_state_adjust_rules()
3083 ps->performance_levels[i].vddci = ps->performance_levels[i - 1].vddci; si_apply_state_adjust_rules()
3097 max_limits->vddci, &ps->performance_levels[i].vddci); si_apply_state_adjust_rules()
3108 max_limits->vddc, max_limits->vddci, si_apply_state_adjust_rules()
3110 &ps->performance_levels[i].vddci); si_apply_state_adjust_rules()
4377 initial_state->performance_levels[0].vddci, si_populate_smc_initial_state()
4378 &table->initialState.levels[0].vddci); si_populate_smc_initial_state()
4506 &table->ACPIState.levels[0].vddci); si_populate_smc_acpi_state()
5001 pl->vddci, &level->vddci); si_convert_power_level_to_smc()
6672 pl->vddci = le16_to_cpu(clock_info->si.usVDDCI); si_parse_pplib_clock_info()
6687 eg_pi->acpi_vddci = pl->vddci; si_parse_pplib_clock_info()
6710 u16 vddc, vddci, mvdd; si_parse_pplib_clock_info() local
6711 radeon_atombios_get_default_voltages(rdev, &vddc, &vddci, &mvdd); si_parse_pplib_clock_info()
6715 pl->vddci = vddci; si_parse_pplib_clock_info()
6724 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = pl->vddci; si_parse_pplib_clock_info()
6998 seq_printf(m, "power level %d sclk: %u mclk: %u vddc: %u vddci: %u pcie gen: %u\n", si_dpm_debugfs_print_current_performance_level()
6999 current_index, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1); si_dpm_debugfs_print_current_performance_level()
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| H A D | rv770_smc.h | 112 RV770_SMC_VOLTAGE_VALUE vddci; member in struct:RV770_SMC_HW_PERFORMANCE_LEVEL
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| H A D | nislands_smc.h | 112 NISLANDS_SMC_VOLTAGE_VALUE vddci; member in struct:NISLANDS_SMC_HW_PERFORMANCE_LEVEL
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| H A D | rv770_dpm.h | 145 u16 vddci; /* eg+ only */ member in struct:rv7xx_pl
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| H A D | sislands_smc.h | 157 SISLANDS_SMC_VOLTAGE_VALUE vddci; member in struct:SISLANDS_SMC_HW_PERFORMANCE_LEVEL
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| H A D | cypress_dpm.c | 751 pl->vddci, cypress_convert_power_level_to_smc()
752 &level->vddci); cypress_convert_power_level_to_smc()
1290 initial_state->low.vddci, cypress_populate_smc_initial_state()
1291 &table->initialState.levels[0].vddci); cypress_populate_smc_initial_state()
1387 &table->ACPIState.levels[0].vddci); cypress_populate_smc_acpi_state()
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| H A D | radeon_atombios.c | 2370 u16 *vddc, u16 *vddci, u16 *mvdd) radeon_atombios_get_default_voltages()
2379 *vddci = 0; radeon_atombios_get_default_voltages()
2389 *vddci = le16_to_cpu(firmware_info->info_22.usBootUpVDDCIVoltage); radeon_atombios_get_default_voltages()
2402 u16 vddc, vddci, mvdd; radeon_atombios_parse_pplib_non_clock_info() local
2404 radeon_atombios_get_default_voltages(rdev, &vddc, &vddci, &mvdd); radeon_atombios_parse_pplib_non_clock_info()
2445 rdev->pm.default_vddci = rdev->pm.power_state[state_index].clock_info[0].voltage.vddci; radeon_atombios_parse_pplib_non_clock_info()
2463 rdev->pm.power_state[state_index].clock_info[j].voltage.vddci = radeon_atombios_parse_pplib_non_clock_info()
2507 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.vddci = radeon_atombios_parse_pplib_clock_info()
2520 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.vddci = radeon_atombios_parse_pplib_clock_info()
3207 u16 *vddc, u16 *vddci, radeon_atom_get_leakage_vddc_based_on_leakage_params()
3219 *vddci = 0; radeon_atom_get_leakage_vddc_based_on_leakage_params()
3270 *vddci = vddci_buf[j * profile->ucElbVDDCI_Num + i]; radeon_atom_get_leakage_vddc_based_on_leakage_params()
2369 radeon_atombios_get_default_voltages(struct radeon_device *rdev, u16 *vddc, u16 *vddci, u16 *mvdd) radeon_atombios_get_default_voltages() argument
3206 radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev, u16 *vddc, u16 *vddci, u16 virtual_voltage_id, u16 vbios_voltage_id) radeon_atom_get_leakage_vddc_based_on_leakage_params() argument
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| H A D | ci_dpm.c | 1333 u16 vddc, vddci; ci_get_leakage_voltages() local
1353 if (radeon_atom_get_leakage_vddc_based_on_leakage_params(rdev, &vddc, &vddci, ci_get_leakage_voltages()
1361 if (vddci != 0 && vddci != virtual_voltage_id) { ci_get_leakage_voltages()
1362 pi->vddci_leakage.actual_voltage[pi->vddci_leakage.count] = vddci; ci_get_leakage_voltages()
4919 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = ci_set_private_data_variables_based_on_pptable()
4939 static void ci_patch_with_vddci_leakage(struct radeon_device *rdev, u16 *vddci) ci_patch_with_vddci_leakage() argument
4946 if (leakage_table->leakage_id[leakage_index] == *vddci) { ci_patch_with_vddci_leakage()
4947 *vddci = leakage_table->actual_voltage[leakage_index]; ci_patch_with_vddci_leakage()
5013 ci_patch_with_vddci_leakage(rdev, (u16 *)&table->vddci); ci_patch_clock_voltage_limits_with_vddc_leakage()
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| H A D | evergreen.c | 1587 * mclk and vddci. evergreen_pm_misc()
1598 if ((voltage->vddci & 0xff00) == 0xff00) evergreen_pm_misc()
1600 if (voltage->vddci && (voltage->vddci != rdev->pm.current_vddci)) { evergreen_pm_misc()
1601 radeon_atom_set_voltage(rdev, voltage->vddci, SET_VOLTAGE_TYPE_ASIC_VDDCI); evergreen_pm_misc()
1602 rdev->pm.current_vddci = voltage->vddci; evergreen_pm_misc()
1603 DRM_DEBUG("Setting: vddci: %d\n", voltage->vddci); evergreen_pm_misc()
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| H A D | radeon.h | 310 u16 *vddc, u16 *vddci,
1278 u8 vddci_id; /* index into vddci voltage table */
1282 /* evergreen+ vddci */
1283 u16 vddci; member in struct:radeon_voltage
1389 u16 vddci; member in struct:radeon_clock_and_voltage_limits
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| H A D | rv6xx_dpm.c | 1865 u16 vddc, vddci, mvdd; rv6xx_parse_pplib_clock_info() local
1866 radeon_atombios_get_default_voltages(rdev, &vddc, &vddci, &mvdd); rv6xx_parse_pplib_clock_info()
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| H A D | radeon_pm.c | 184 * mclk and vddci. radeon_set_power_state()
1238 rdev->pm.current_vddci = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.vddci; radeon_pm_resume_old()
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| H A D | r600_dpm.c | 978 rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddci = r600_parse_extended_power_table()
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| H A D | radeon_mode.h | 718 u16 *vddc, u16 *vddci, u16 *mvdd);
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