Searched refs:transfer (Results 1 - 200 of 1932) sorted by relevance

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/linux-4.1.27/drivers/net/ethernet/qualcomm/
H A Dqca_7k.c50 struct spi_transfer *transfer; qcaspi_read_register() local
58 transfer = &qca->spi_xfer1; qcaspi_read_register()
59 transfer->tx_buf = &tx_data; qcaspi_read_register()
60 transfer->rx_buf = NULL; qcaspi_read_register()
61 transfer->len = QCASPI_CMD_LEN; qcaspi_read_register()
65 transfer = &qca->spi_xfer2[0]; qcaspi_read_register()
66 transfer->tx_buf = &tx_data; qcaspi_read_register()
67 transfer->rx_buf = NULL; qcaspi_read_register()
68 transfer->len = QCASPI_CMD_LEN; qcaspi_read_register()
69 transfer = &qca->spi_xfer2[1]; qcaspi_read_register()
71 transfer->tx_buf = NULL; qcaspi_read_register()
72 transfer->rx_buf = &rx_data; qcaspi_read_register()
73 transfer->len = QCASPI_CMD_LEN; qcaspi_read_register()
91 struct spi_transfer *transfer; qcaspi_write_register() local
100 transfer = &qca->spi_xfer1; qcaspi_write_register()
101 transfer->tx_buf = &tx_data[0]; qcaspi_write_register()
102 transfer->rx_buf = NULL; qcaspi_write_register()
103 transfer->len = QCASPI_CMD_LEN; qcaspi_write_register()
107 transfer = &qca->spi_xfer2[0]; qcaspi_write_register()
108 transfer->tx_buf = &tx_data[0]; qcaspi_write_register()
109 transfer->rx_buf = NULL; qcaspi_write_register()
110 transfer->len = QCASPI_CMD_LEN; qcaspi_write_register()
111 transfer = &qca->spi_xfer2[1]; qcaspi_write_register()
113 transfer->tx_buf = &tx_data[1]; qcaspi_write_register()
114 transfer->rx_buf = NULL; qcaspi_write_register()
115 transfer->len = QCASPI_CMD_LEN; qcaspi_write_register()
132 struct spi_transfer *transfer = &qca->spi_xfer1; qcaspi_tx_cmd() local
136 transfer->len = sizeof(tx_data); qcaspi_tx_cmd()
137 transfer->tx_buf = &tx_data; qcaspi_tx_cmd()
138 transfer->rx_buf = NULL; qcaspi_tx_cmd()
H A Dqca_spi.c104 struct spi_transfer *transfer = &qca->spi_xfer2[0]; qcaspi_write_burst() local
108 transfer->tx_buf = &cmd; qcaspi_write_burst()
109 transfer->rx_buf = NULL; qcaspi_write_burst()
110 transfer->len = QCASPI_CMD_LEN; qcaspi_write_burst()
111 transfer = &qca->spi_xfer2[1]; qcaspi_write_burst()
112 transfer->tx_buf = src; qcaspi_write_burst()
113 transfer->rx_buf = NULL; qcaspi_write_burst()
114 transfer->len = len; qcaspi_write_burst()
130 struct spi_transfer *transfer = &qca->spi_xfer1; qcaspi_write_legacy() local
133 transfer->tx_buf = src; qcaspi_write_legacy()
134 transfer->rx_buf = NULL; qcaspi_write_legacy()
135 transfer->len = len; qcaspi_write_legacy()
152 struct spi_transfer *transfer = &qca->spi_xfer2[0]; qcaspi_read_burst() local
156 transfer->tx_buf = &cmd; qcaspi_read_burst()
157 transfer->rx_buf = NULL; qcaspi_read_burst()
158 transfer->len = QCASPI_CMD_LEN; qcaspi_read_burst()
159 transfer = &qca->spi_xfer2[1]; qcaspi_read_burst()
160 transfer->tx_buf = NULL; qcaspi_read_burst()
161 transfer->rx_buf = dst; qcaspi_read_burst()
162 transfer->len = len; qcaspi_read_burst()
178 struct spi_transfer *transfer = &qca->spi_xfer1; qcaspi_read_legacy() local
181 transfer->tx_buf = NULL; qcaspi_read_legacy()
182 transfer->rx_buf = dst; qcaspi_read_legacy()
183 transfer->len = len; qcaspi_read_legacy()
/linux-4.1.27/arch/m32r/include/asm/
H A Ddma.h7 * The maximum address that we can perform a DMA transfer
/linux-4.1.27/arch/avr32/include/asm/
H A Ddma.h4 /* The maximum address that we can perform a DMA transfer to on this platform.
H A Dcache.h11 * cache before the transfer is done, causing old data to be seen by
H A Ddma-mapping.h108 * @dir: DMA transfer direction
129 * @dir: DMA transfer direction
151 * @dir: DMA transfer direction
173 * @dir: DMA transfer direction
194 * @dir: DMA transfer direction
233 * @dir: DMA transfer direction
251 * @dir: DMA transfer direction
254 * translation after a transfer.
304 * @dir: DMA transfer direction
307 * mode DMA translations after a transfer.
/linux-4.1.27/sound/core/
H A Disadma.c34 * snd_dma_program - program an ISA DMA transfer
37 * @size: the DMA transfer size
38 * @mode: the DMA transfer mode, DMA_MODE_XXX
40 * Programs an ISA DMA transfer for the given buffer.
62 * snd_dma_disable - stop the ISA DMA transfer
65 * Stops the ISA DMA transfer.
80 * snd_dma_pointer - return the current pointer to DMA transfer buffer in bytes
82 * @size: the dma transfer size
84 * Return: The current pointer in DMA transfer buffer in bytes.
109 pr_err("ALSA: pointer (0x%x) for DMA #%ld is greater than transfer size (0x%x)\n", result, dma, size); snd_dma_pointer()
/linux-4.1.27/arch/mn10300/proc-mn103e010/include/proc/
H A Ddmactl-regs.h21 #define DMxCTR_BG 0x0000001f /* transfer request source */
42 #define DMxCTR_SAM 0x000000e0 /* DMA transfer src addr mode */
46 #define DMxCTR_DAM 0x00000000 /* DMA transfer dest addr mode */
50 #define DMxCTR_TM 0x00001800 /* DMA transfer mode */
51 #define DMxCTR_TM_BATCH 0x00000000 /* - batch transfer */
52 #define DMxCTR_TM_INTERM 0x00001000 /* - intermittent transfer */
53 #define DMxCTR_UT 0x00006000 /* DMA transfer unit */
58 #define DMxCTR_TEN 0x00010000 /* DMA channel transfer enable */
64 #define DMxCTR_RQF 0x01000000 /* DMA transfer request flag */
65 #define DMxCTR_XEND 0x80000000 /* DMA transfer end flag */
72 #define DMxSIZ_CT 0x000fffff /* number of bytes to transfer */
/linux-4.1.27/include/linux/
H A Deeprom_93xx46.h14 * before and after spi transfer.
H A Dshdma-base.h26 * SHDMA_PM_ESTABLISHED: either idle or during data transfer
27 * SHDMA_PM_BUSY: during the transfer preparation, when we have to
57 bool cyclic; /* used as cyclic transfer */
68 size_t max_xfer_len; /* max transfer length */
88 * start_xfer: start the DMA transfer (atomic)
91 * chan_irq: process channel IRQ, return true if a transfer has
H A Dcb710.h150 * Best-case reading (transfer from device):
155 * Best-case writing (transfer to device):
165 * cb710_sg_dwiter_write_from_io - transfer data to mapped buffer from 32-bit IO port
168 * @count: number of 32-bit words to transfer
187 * cb710_sg_dwiter_read_to_io - transfer data to 32-bit IO port from mapped buffer
190 * @count: number of 32-bit words to transfer
H A Dvia-core.h128 #define VDE_I_DMA0TDONE 0x00000020 /* DMA 0 transfer done */
130 #define VDE_I_DMA1TDONE 0x00000080 /* DMA 1 transfer done */
173 #define VDMA_C_START 0x02 /* Start a transfer */
174 #define VDMA_C_ABORT 0x04 /* Abort a transfer */
182 #define VDMA_DPR_IN 0x08 /* Inbound transfer to FB */
H A Di2c-gpio.h19 * SCL low for longer than this, the transfer will time out.
H A Ddmaengine.h80 * enum dma_transfer_direction - dma transfer mode and direction indicator
101 * that when repeated an integral number of times, specifies the transfer.
102 * A transfer template is specification of a Frame, the number of times
103 * it is to be repeated and other per-transfer attributes.
106 * type of transfer it is going to need during its lifetime and
132 * struct dma_interleaved_template - Template to convey DMAC the transfer pattern
341 * enum dma_residue_granularity - Granularity of the reported transfer residue
347 * completed segment of the transfer (For cyclic transfers this is after each
376 * @residue_granularity: granularity of the reported transfer residue
548 * a transfer.
552 * on the selected transfer for states DMA_IN_PROGRESS and
581 * @residue_granularity: granularity of the transfer residue reported
599 * @device_pause: Pauses any transfer happening on a channel. Returns
601 * @device_resume: Resumes any transfer on a channel previously
607 * struct with auxiliary transfer status information, otherwise the call
/linux-4.1.27/drivers/usb/chipidea/
H A Dudc.h22 /* DMA layout of transfer descriptors */
73 * @ptr: transfer descriptor for this request
74 * @dma: dma address for the transfer descriptor
75 * @zptr: transfer descriptor for the zero packet
76 * @zdma: dma address of the zero packet's transfer descriptor
/linux-4.1.27/drivers/spi/
H A Dspi-mpc52xx.c80 /* Details of current transfer (length, and buffer pointers) */
82 struct spi_transfer *transfer; /* current transfer */ member in struct:mpc52xx_spi
108 * Start a new transfer. This is called both by the idle state
109 * for the first transfer in a message, and by the wait state when the
110 * previous transfer in a message is complete.
114 ms->rx_buf = ms->transfer->rx_buf; mpc52xx_spi_start_transfer()
115 ms->tx_buf = ms->transfer->tx_buf; mpc52xx_spi_start_transfer()
116 ms->len = ms->transfer->len; mpc52xx_spi_start_transfer()
121 ms->cs_change = ms->transfer->cs_change; mpc52xx_spi_start_transfer()
140 * No transfers are in progress; if another transfer is pending then retrieve
154 /* Check if there is another transfer waiting. */ mpc52xx_spi_fsmstate_idle()
193 ms->transfer = container_of(ms->message->transfers.next, mpc52xx_spi_fsmstate_idle()
205 * In the middle of a transfer. If the SPI core has completed processing
207 * (unless this transfer is finished; in which case go on to the wait
223 * transfer which is what we do here. */ mpc52xx_spi_fsmstate_transfer()
248 /* Is the transfer complete? */ mpc52xx_spi_fsmstate_transfer()
252 ms->timestamp += ms->transfer->delay_usecs * tb_ticks_per_usec; mpc52xx_spi_fsmstate_transfer()
270 * A transfer has completed; need to wait for the delay period to complete
271 * before starting the next transfer
283 ms->message->actual_length += ms->transfer->len; mpc52xx_spi_fsmstate_wait()
285 /* Check if there is another transfer in this message. If there mpc52xx_spi_fsmstate_wait()
288 if (ms->transfer->transfer_list.next == &ms->message->transfers) { mpc52xx_spi_fsmstate_wait()
298 /* There is another transfer; kick it off */ mpc52xx_spi_fsmstate_wait()
303 ms->transfer = container_of(ms->transfer->transfer_list.next, mpc52xx_spi_fsmstate_wait()
423 master->transfer = mpc52xx_spi_transfer; mpc52xx_spi_probe()
H A Dspi-bfin-sport.c78 /* Current message transfer state info */
268 /* test if there is more transfer to be done */
275 /* Move to next transfer */ bfin_sport_spi_next_transfer()
342 struct spi_transfer *transfer = NULL; bfin_sport_spi_pump_transfers() local
352 transfer = drv_data->cur_transfer; bfin_sport_spi_pump_transfers()
355 if (transfer->speed_hz) bfin_sport_spi_pump_transfers()
356 transfer_speed = bfin_sport_hz_to_spi_baud(transfer->speed_hz); bfin_sport_spi_pump_transfers()
368 dev_dbg(drv_data->dev, "transfer: we've hit an error\n"); bfin_sport_spi_pump_transfers()
376 dev_dbg(drv_data->dev, "transfer: all done!\n"); bfin_sport_spi_pump_transfers()
382 /* Delay if requested at end of transfer */ bfin_sport_spi_pump_transfers()
384 dev_dbg(drv_data->dev, "transfer: still running ...\n"); bfin_sport_spi_pump_transfers()
385 previous = list_entry(transfer->transfer_list.prev, bfin_sport_spi_pump_transfers()
391 if (transfer->len == 0) { bfin_sport_spi_pump_transfers()
392 /* Move to next transfer of this msg */ bfin_sport_spi_pump_transfers()
394 /* Schedule next transfer tasklet */ bfin_sport_spi_pump_transfers()
398 if (transfer->tx_buf != NULL) { bfin_sport_spi_pump_transfers()
399 drv_data->tx = (void *)transfer->tx_buf; bfin_sport_spi_pump_transfers()
400 drv_data->tx_end = drv_data->tx + transfer->len; bfin_sport_spi_pump_transfers()
402 transfer->tx_buf, drv_data->tx_end); bfin_sport_spi_pump_transfers()
406 if (transfer->rx_buf != NULL) { bfin_sport_spi_pump_transfers()
407 full_duplex = transfer->tx_buf != NULL; bfin_sport_spi_pump_transfers()
408 drv_data->rx = transfer->rx_buf; bfin_sport_spi_pump_transfers()
409 drv_data->rx_end = drv_data->rx + transfer->len; bfin_sport_spi_pump_transfers()
411 transfer->rx_buf, drv_data->rx_end); bfin_sport_spi_pump_transfers()
415 drv_data->cs_change = transfer->cs_change; bfin_sport_spi_pump_transfers()
418 bits_per_word = transfer->bits_per_word; bfin_sport_spi_pump_transfers()
433 "now pumping a transfer: width is %d, len is %d\n", bfin_sport_spi_pump_transfers()
434 bits_per_word, transfer->len); bfin_sport_spi_pump_transfers()
437 dev_dbg(drv_data->dev, "doing IO transfer\n"); bfin_sport_spi_pump_transfers()
469 message->actual_length += transfer->len; bfin_sport_spi_pump_transfers()
470 /* Move to next transfer of this msg */ bfin_sport_spi_pump_transfers()
476 /* Schedule next transfer tasklet */ bfin_sport_spi_pump_transfers()
480 /* pop a msg from queue and kick off real transfer */
527 "the first transfer len is %d\n", bfin_sport_spi_pump_messages()
538 * got a msg to transfer, queue it in drv_data->queue.
558 dev_dbg(&spi->dev, "adding an msg in transfer()\n"); bfin_sport_spi_transfer()
668 /* init transfer tasklet */ bfin_sport_spi_init_queue()
778 master->transfer = bfin_sport_spi_transfer; bfin_sport_spi_probe()
H A Dspi-bfin5xx.c81 /* Current message transfer state info */
221 /* used to kick off transfer in rx mode and read unwanted RX data */ bfin_spi_dummy_read()
234 /* wait until transfer finished. bfin_spi_u8_writer()
235 checking SPIF or TXS may not guarantee transfer completion */ bfin_spi_u8_writer()
285 /* wait until transfer finished. bfin_spi_u16_writer()
286 checking SPIF or TXS may not guarantee transfer completion */ bfin_spi_u16_writer()
331 /* test if there is more transfer to be done */ bfin_spi_next_transfer()
337 /* Move to next transfer */ bfin_spi_next_transfer()
387 /* wait until transfer finished. */ bfin_spi_pio_irq_handler()
411 /* Move to next transfer */ bfin_spi_pio_irq_handler()
416 /* Schedule transfer tasklet */ bfin_spi_pio_irq_handler()
538 /* Move to next transfer */ bfin_spi_dma_irq_handler()
542 /* Schedule transfer tasklet */ bfin_spi_dma_irq_handler()
545 /* free the irq handler before next transfer */ bfin_spi_dma_irq_handler()
558 struct spi_transfer *transfer = NULL; bfin_spi_pump_transfers() local
568 transfer = drv_data->cur_transfer; bfin_spi_pump_transfers()
577 dev_dbg(&drv_data->pdev->dev, "transfer: we've hit an error\n"); bfin_spi_pump_transfers()
585 dev_dbg(&drv_data->pdev->dev, "transfer: all done!\n"); bfin_spi_pump_transfers()
592 /* Delay if requested at end of transfer */ bfin_spi_pump_transfers()
594 dev_dbg(&drv_data->pdev->dev, "transfer: still running ...\n"); bfin_spi_pump_transfers()
595 previous = list_entry(transfer->transfer_list.prev, bfin_spi_pump_transfers()
609 if (transfer->len == 0) { bfin_spi_pump_transfers()
610 /* Move to next transfer of this msg */ bfin_spi_pump_transfers()
612 /* Schedule next transfer tasklet */ bfin_spi_pump_transfers()
617 if (transfer->tx_buf != NULL) { bfin_spi_pump_transfers()
618 drv_data->tx = (void *)transfer->tx_buf; bfin_spi_pump_transfers()
619 drv_data->tx_end = drv_data->tx + transfer->len; bfin_spi_pump_transfers()
621 transfer->tx_buf, drv_data->tx_end); bfin_spi_pump_transfers()
626 if (transfer->rx_buf != NULL) { bfin_spi_pump_transfers()
627 full_duplex = transfer->tx_buf != NULL; bfin_spi_pump_transfers()
628 drv_data->rx = transfer->rx_buf; bfin_spi_pump_transfers()
629 drv_data->rx_end = drv_data->rx + transfer->len; bfin_spi_pump_transfers()
631 transfer->rx_buf, drv_data->rx_end); bfin_spi_pump_transfers()
636 drv_data->rx_dma = transfer->rx_dma; bfin_spi_pump_transfers()
637 drv_data->tx_dma = transfer->tx_dma; bfin_spi_pump_transfers()
638 drv_data->len_in_bytes = transfer->len; bfin_spi_pump_transfers()
639 drv_data->cs_change = transfer->cs_change; bfin_spi_pump_transfers()
642 bits_per_word = transfer->bits_per_word; bfin_spi_pump_transfers()
645 drv_data->len = (transfer->len) >> 1; bfin_spi_pump_transfers()
650 drv_data->len = transfer->len; bfin_spi_pump_transfers()
658 "transfer: drv_data->ops is %p, chip->ops is %p, u8_ops is %p\n", bfin_spi_pump_transfers()
665 if (transfer->speed_hz) bfin_spi_pump_transfers()
666 bfin_write(&drv_data->regs->baud, hz_to_spi_baud(transfer->speed_hz)); bfin_spi_pump_transfers()
674 "now pumping a transfer: width is %d, len is %d\n", bfin_spi_pump_transfers()
675 cr_width, transfer->len); bfin_spi_pump_transfers()
678 * Try to map dma buffer and do a dma transfer. If successful use, bfin_spi_pump_transfers()
680 * we are not doing a full duplex transfer (since the hardware does bfin_spi_pump_transfers()
692 dev_dbg(&drv_data->pdev->dev, "doing dma transfer\n"); bfin_spi_pump_transfers()
719 /* start SPI transfer */ bfin_spi_pump_transfers()
722 /* just return here, there can only be one transfer bfin_spi_pump_transfers()
730 /* In dma mode, rx or tx must be NULL in one transfer */ bfin_spi_pump_transfers()
733 /* set transfer mode, and enable SPI */ bfin_spi_pump_transfers()
784 * We always use SPI_WRITE mode (transfer starts with TDBR write). bfin_spi_pump_transfers()
785 * SPI_READ mode (transfer starts with RDBR read) seems to have bfin_spi_pump_transfers()
787 * start of the transfer. bfin_spi_pump_transfers()
797 /* start transfer */ bfin_spi_pump_transfers()
823 dev_dbg(&drv_data->pdev->dev, "doing IO transfer\n"); bfin_spi_pump_transfers()
862 /* Move to next transfer of this msg */ bfin_spi_pump_transfers()
870 /* Schedule next transfer tasklet */ bfin_spi_pump_transfers()
874 /* pop a msg from queue and kick off real transfer */ bfin_spi_pump_messages()
919 "the first transfer len is %d\n", bfin_spi_pump_messages()
930 * got a msg to transfer, queue it in drv_data->queue.
949 dev_dbg(&spi->dev, "adding an msg in transfer() \n"); bfin_spi_transfer()
1180 /* init transfer tasklet */ bfin_spi_init_queue()
1289 master->transfer = bfin_spi_transfer; bfin_spi_probe()
H A Dspi-dw.c190 /* Set the tx word if the transfer's original "tx" is not null */ dw_writer()
209 /* Care rx only if the transfer's original "rx" is not null */ dw_reader()
286 struct spi_device *spi, struct spi_transfer *transfer) dw_spi_transfer_one()
301 dws->tx = (void *)transfer->tx_buf; dw_spi_transfer_one()
302 dws->tx_end = dws->tx + transfer->len; dw_spi_transfer_one()
303 dws->rx = transfer->rx_buf; dw_spi_transfer_one()
304 dws->rx_end = dws->rx + transfer->len; dw_spi_transfer_one()
305 dws->len = transfer->len; dw_spi_transfer_one()
311 /* Handle per transfer options for bpw and speed */ dw_spi_transfer_one()
312 if (transfer->speed_hz) { dw_spi_transfer_one()
315 if ((transfer->speed_hz != speed) || !chip->clk_div) { dw_spi_transfer_one()
316 speed = transfer->speed_hz; dw_spi_transfer_one()
327 if (transfer->bits_per_word) { dw_spi_transfer_one()
328 if (transfer->bits_per_word == 8) { dw_spi_transfer_one()
331 } else if (transfer->bits_per_word == 16) { dw_spi_transfer_one()
335 cr0 = (transfer->bits_per_word - 1) dw_spi_transfer_one()
342 * Adjust transfer mode if necessary. Requires platform dependent dw_spi_transfer_one()
359 /* Check if current transfer is a DMA transaction */ dw_spi_transfer_one()
360 if (master->can_dma && master->can_dma(master, spi, transfer)) dw_spi_transfer_one()
371 ret = dws->dma_ops->dma_setup(dws, transfer); dw_spi_transfer_one()
391 ret = dws->dma_ops->dma_transfer(dws, transfer); dw_spi_transfer_one()
285 dw_spi_transfer_one(struct spi_master *master, struct spi_device *spi, struct spi_transfer *transfer) dw_spi_transfer_one() argument
H A Dspi-cadence.c110 * @tx_bytes: Number of bytes left to transfer
242 * @transfer: Pointer to the spi_transfer structure which provides
243 * information about next transfer setup parameters
248 * is lower than the requested frequency (maximum lower) for the transfer. If
254 struct spi_transfer *transfer) cdns_spi_config_clock_freq()
265 if (xspi->speed_hz != transfer->speed_hz) { cdns_spi_config_clock_freq()
269 (frequency / (2 << baud_rate_val)) > transfer->speed_hz) cdns_spi_config_clock_freq()
281 * cdns_spi_setup_transfer - Configure SPI controller for specified transfer
283 * @transfer: Pointer to the spi_transfer structure which provides
284 * information about next transfer setup parameters
286 * Sets the operational mode of SPI controller for the next SPI transfer and
292 struct spi_transfer *transfer) cdns_spi_setup_transfer()
296 cdns_spi_config_clock_freq(spi, transfer); cdns_spi_setup_transfer()
334 * On Mode Fault interrupt this function indicates that transfer is completed,
351 /* Indicate that transfer is completed, the SPI subsystem will cdns_spi_irq()
398 * cdns_transfer_one - Initiates the SPI transfer
401 * @transfer: Pointer to the spi_transfer structure which provides
402 * information about next transfer parameters
404 * This function fills the TX FIFO, starts the SPI transfer and
405 * returns a positive transfer count so that core will wait for completion.
407 * Return: Number of bytes transferred in the last transfer
411 struct spi_transfer *transfer) cdns_transfer_one()
415 xspi->txbuf = transfer->tx_buf; cdns_transfer_one()
416 xspi->rxbuf = transfer->rx_buf; cdns_transfer_one()
417 xspi->tx_bytes = transfer->len; cdns_transfer_one()
418 xspi->rx_bytes = transfer->len; cdns_transfer_one()
420 cdns_spi_setup_transfer(spi, transfer); cdns_transfer_one()
426 return transfer->len; cdns_transfer_one()
430 * cdns_prepare_transfer_hardware - Prepares hardware for transfer.
449 * cdns_unprepare_transfer_hardware - Relaxes hardware after transfer
253 cdns_spi_config_clock_freq(struct spi_device *spi, struct spi_transfer *transfer) cdns_spi_config_clock_freq() argument
291 cdns_spi_setup_transfer(struct spi_device *spi, struct spi_transfer *transfer) cdns_spi_setup_transfer() argument
409 cdns_transfer_one(struct spi_master *master, struct spi_device *spi, struct spi_transfer *transfer) cdns_transfer_one() argument
H A Dspi-fsl-dspi.c227 /* If we are in word mode, but only have a single byte to transfer dspi_transfer_write()
229 * end of the transfer. dspi_transfer_write()
274 /* last transfer in the transfer */ dspi_transfer_write()
335 struct spi_transfer *transfer; dspi_transfer_one_message() local
339 list_for_each_entry(transfer, &message->transfers, transfer_list) { dspi_transfer_one_message()
340 dspi->cur_transfer = transfer; dspi_transfer_one_message()
346 transfer->cs_change = 1; dspi_transfer_one_message()
347 dspi->cs_change = transfer->cs_change; dspi_transfer_one_message()
351 dspi->tx = (void *)transfer->tx_buf; dspi_transfer_one_message()
352 dspi->tx_end = dspi->tx + transfer->len; dspi_transfer_one_message()
353 dspi->rx = transfer->rx_buf; dspi_transfer_one_message()
354 dspi->rx_end = dspi->rx + transfer->len; dspi_transfer_one_message()
355 dspi->len = transfer->len; dspi_transfer_one_message()
369 if (transfer->speed_hz) dspi_transfer_one_message()
377 dev_err(&dspi->pdev->dev, "wait transfer complete fail!\n"); dspi_transfer_one_message()
380 if (transfer->delay_usecs) dspi_transfer_one_message()
381 udelay(transfer->delay_usecs); dspi_transfer_one_message()
538 master->transfer = NULL; dspi_probe()
H A Dspi-s3c24xx-fiq.h6 * S3C24XX SPI - FIQ pseudo-DMA transfer support
H A Dspi-ep93xx.c76 * @wait: wait here until given transfer is completed
78 * @tx: current byte in transfer to transmit
79 * @rx: current byte in transfer to receive
307 * @speed_hz: transfer speed
308 * @bits_per_word: transfer bits_per_word
377 * ep93xx_spi_read_write() - perform next RX/TX transfer
381 * called several times, the whole transfer will be completed. Returns
382 * %-EINPROGRESS when current transfer was not yet completed otherwise %0.
413 * Now everything is set up for the current transfer. We prime the TX ep93xx_spi_pio_transfer()
414 * FIFO, enable interrupts, and wait for the transfer to complete. ep93xx_spi_pio_transfer()
423 * ep93xx_spi_dma_prepare() - prepares a DMA transfer
425 * @dir: DMA transfer direction
474 * We need to split the transfer into PAGE_SIZE'd chunks. This is ep93xx_spi_dma_prepare()
526 * ep93xx_spi_dma_finish() - finishes with a DMA transfer
528 * @dir: DMA transfer direction
530 * Function finishes with the DMA transfer. After this, the DMA buffer is
593 * ep93xx_spi_process_transfer() - processes one SPI transfer
596 * @t: transfer to process
598 * This function processes one SPI transfer given in @t. Function waits until
599 * transfer is complete (may sleep) and updates @msg->status based on whether
600 * transfer was successfully processed or not.
614 "failed to setup chip for transfer\n"); ep93xx_spi_process_transfer()
642 * After this transfer is finished, perform any possible ep93xx_spi_process_transfer()
643 * post-transfer actions requested by the protocol driver. ep93xx_spi_process_transfer()
670 * asserted during the whole message (unless per transfer cs_change is set).
767 * simply execute next data transfer. ep93xx_spi_interrupt()
772 * for current transfer. Let's wait for the next ep93xx_spi_interrupt()
780 * Current transfer is finished, either with error or with success. In ep93xx_spi_interrupt()
H A Dspi-meson-spifc.c191 * meson_spifc_txrx() - transfer a chunk of data
193 * @xfer: the current SPI transfer
194 * @offset: offset of the data to transfer
195 * @len: length of the data to transfer
196 * @last_xfer: whether this is the last transfer of the message
197 * @last_chunk: whether this is the last chunk of the transfer
233 /* start transfer */ meson_spifc_txrx()
245 * meson_spifc_transfer_one() - perform a single transfer
248 * @xfer: the current SPI transfer
H A Dspi-topcliff-pch.c147 * @transfer_active: Flag showing active transfer
149 * transfer
151 * transfer
160 * @cur_trans: The current transfer that this SPI driver is
318 /* if transfer complete interrupt */ pch_spi_handler_sub()
325 /* transfer is completed; pch_spi_handler_sub()
410 * @bits_per_word: Bits per word for SPI transfer.
422 * pch_spi_setup_transfer() - Configures the PCH SPI hardware for transfer
466 struct spi_transfer *transfer; pch_spi_transfer() local
473 list_for_each_entry(transfer, &pmsg->transfers, transfer_list) { pch_spi_transfer()
474 if (!transfer->tx_buf && !transfer->rx_buf) { pch_spi_transfer()
481 if (!transfer->len) { pch_spi_transfer()
639 /* reset transfer complete flag */ pch_spi_set_tx()
649 * [To the spi core..indicating end of transfer] */ pch_spi_nomore_transfer()
713 /* Wait until the transfer completes; go to sleep after pch_spi_set_ir()
714 initiating the transfer. */ pch_spi_set_ir()
716 "%s:waiting for transfer to get over\n", __func__); pch_spi_set_ir()
723 /* Disable interrupts and SPI transfer */ pch_spi_set_ir()
792 /* Wait until the transfer completes; go to sleep after pch_spi_start_transfer()
793 initiating the transfer. */ pch_spi_start_transfer()
795 "%s:waiting for transfer to get over\n", __func__); pch_spi_start_transfer()
817 /* clear fifo threshold, disable interrupts, disable SPI transfer */ pch_spi_start_transfer()
836 /* transfer is completed;inform pch_spi_process_messages_dma */ pch_dma_rx_complete()
1123 /* reset transfer complete flag */ pch_spi_handle_dma()
1181 transfer structure from the message otherwise retrieve pch_spi_process_messages()
1182 the 1st transfer request from the message. */ pch_spi_process_messages()
1189 ":Getting 1st transfer message\n", __func__); pch_spi_process_messages()
1195 ":Getting next transfer message\n", __func__); pch_spi_process_messages()
1248 /* No more transfer in this message. */ pch_spi_process_messages()
1381 master->transfer = pch_spi_transfer; pch_spi_pd_probe()
1500 Only after thats done the transfer will be suspended */ pch_spi_pd_suspend()
H A Dspi-pxa2xx.c412 /* Move to next transfer */ pxa2xx_spi_next_transfer()
518 /* Move to next transfer */ int_transfer_complete()
521 /* Schedule transfer tasklet */ int_transfer_complete()
810 struct spi_transfer *transfer = NULL; pump_transfers() local
824 transfer = drv_data->cur_transfer; pump_transfers()
841 /* Delay if requested at end of transfer before CS change */ pump_transfers()
843 previous = list_entry(transfer->transfer_list.prev, pump_transfers()
854 /* Check if we can DMA this transfer */ pump_transfers()
855 if (!pxa2xx_spi_dma_is_possible(transfer->len) && chip->enable_dma) { pump_transfers()
859 || transfer->rx_dma || transfer->tx_dma) { pump_transfers()
861 "pump_transfers: mapped transfer length of " pump_transfers()
863 transfer->len, MAX_DMA_LEN); pump_transfers()
871 "pump_transfers: DMA disabled for transfer length %ld " pump_transfers()
876 /* Setup the transfer state based on the type of transfer */ pump_transfers()
884 drv_data->tx = (void *)transfer->tx_buf; pump_transfers()
885 drv_data->tx_end = drv_data->tx + transfer->len; pump_transfers()
886 drv_data->rx = transfer->rx_buf; pump_transfers()
887 drv_data->rx_end = drv_data->rx + transfer->len; pump_transfers()
888 drv_data->rx_dma = transfer->rx_dma; pump_transfers()
889 drv_data->tx_dma = transfer->tx_dma; pump_transfers()
890 drv_data->len = transfer->len; pump_transfers()
894 /* Change speed and bit per word on a per transfer */ pump_transfers()
896 if (transfer->speed_hz || transfer->bits_per_word) { pump_transfers()
901 if (transfer->speed_hz) pump_transfers()
902 speed = transfer->speed_hz; pump_transfers()
904 if (transfer->bits_per_word) pump_transfers()
905 bits = transfer->bits_per_word; pump_transfers()
H A Dspi-davinci.c275 * davinci_spi_setup_transfer - This functions will determine transfer method
276 * @spi: spi device on which data transfer to be done
277 * @t: spi transfer in which transfer info is filled
279 * This function determines data transfer method (8/16/32 bit transfer).
308 * Assign function pointer to appropriate transfer method davinci_spi_setup_transfer()
309 * 8bit, 16bit or 32bit transfer davinci_spi_setup_transfer()
418 * davinci_spi_setup - This functions will set default transfer method
419 * @spi: spi device on which data transfer to be done
421 * This functions sets the default transfer method.
576 * davinci_spi_bufs - functions which will handle transfer data
577 * @spi: spi device on which data transfer to be done
578 * @t: spi transfer in which transfer info is filled
621 /* start the transfer */ davinci_spi_bufs()
708 /* Wait for the transfer to complete */ davinci_spi_bufs()
746 dev_err(&spi->dev, "SPI data transfer error\n"); davinci_spi_bufs()
782 * transfer length and if it is not zero then dispatch transfer command again.
783 * If transfer length is zero then it will indicate the COMPLETION so that
907 * can register transfer method to work queue.
H A Dspi-bcm63xx.c185 /* Issue the transfer */ bcm63xx_txrx_bufs()
230 * transfer. bcm63xx_spi_transfer_one()
247 /* we can only transfer one fifo worth of data */ bcm63xx_spi_transfer_one()
264 /* CS will be deasserted directly after transfer */ bcm63xx_spi_transfer_one()
266 dev_err(&spi->dev, "unable to keep CS asserted after transfer\n"); bcm63xx_spi_transfer_one()
273 /* configure adapter for a new transfer */ bcm63xx_spi_transfer_one()
310 /* A transfer completed */ bcm63xx_spi_interrupt()
H A Dspi-bitbang.c244 * SECOND PART ... simple transfer queue runner.
247 * performing each transfer in sequence. Smarter hardware can queue
252 * transfer-at-a-time ones to leverage dma or fifo hardware.
297 /* init (-1) or override (1) transfer params */ spi_bitbang_transfer_one()
324 /* transfer data. the lower level code handles any spi_bitbang_transfer_one()
346 /* protocol tweaks before next transfer */ spi_bitbang_transfer_one()
400 * a transfer method, its final step should call spi_bitbang_transfer; or,
401 * that's the default if the transfer routine is not initialized. It should
435 if (master->transfer || master->transfer_one_message) spi_bitbang_start()
H A Dspi-imx.c57 /* The maximum bytes that a sdma BD can transfer.*/
200 struct spi_transfer *transfer) spi_imx_can_dma()
205 && transfer->len > spi_imx->rx_wml * sizeof(u32) spi_imx_can_dma()
206 && transfer->len > spi_imx->tx_wml * sizeof(u32)) spi_imx_can_dma()
783 /* Initialize the functions for transfer */ spi_imx_setupxfer()
895 struct spi_transfer *transfer) spi_imx_dma_transfer()
903 struct sg_table *tx = &transfer->tx_sg, *rx = &transfer->rx_sg; spi_imx_dma_transfer()
938 left = transfer->len % spi_imx->rxt_wml; spi_imx_dma_transfer()
946 /* Wait SDMA to finish the data transfer.*/ spi_imx_dma_transfer()
975 ret = transfer->len; spi_imx_dma_transfer()
987 struct spi_transfer *transfer) spi_imx_pio_transfer()
991 spi_imx->tx_buf = transfer->tx_buf; spi_imx_pio_transfer()
992 spi_imx->rx_buf = transfer->rx_buf; spi_imx_pio_transfer()
993 spi_imx->count = transfer->len; spi_imx_pio_transfer()
1004 return transfer->len; spi_imx_pio_transfer()
1008 struct spi_transfer *transfer) spi_imx_transfer()
1014 spi_imx_can_dma(spi_imx->bitbang.master, spi, transfer)) { spi_imx_transfer()
1016 ret = spi_imx_dma_transfer(spi_imx, transfer); spi_imx_transfer()
1022 return spi_imx_pio_transfer(spi, transfer); spi_imx_transfer()
199 spi_imx_can_dma(struct spi_master *master, struct spi_device *spi, struct spi_transfer *transfer) spi_imx_can_dma() argument
894 spi_imx_dma_transfer(struct spi_imx_data *spi_imx, struct spi_transfer *transfer) spi_imx_dma_transfer() argument
986 spi_imx_pio_transfer(struct spi_device *spi, struct spi_transfer *transfer) spi_imx_pio_transfer() argument
1007 spi_imx_transfer(struct spi_device *spi, struct spi_transfer *transfer) spi_imx_transfer() argument
H A Dspi-pxa2xx-pxadma.c32 /* Try to map dma buffer and do a dma transfer if successful, but pxa2xx_spi_dma_is_possible()
36 * of PIO instead. Care is needed above because the transfer may pxa2xx_spi_dma_is_possible()
38 * A zero-length transfer in PIO mode will not try to write/read pxa2xx_spi_dma_is_possible()
201 /* Move to next transfer */ pxa2xx_spi_dma_transfer_complete()
204 /* Schedule transfer tasklet */ pxa2xx_spi_dma_transfer_complete()
234 /* finish this transfer, start the next */ pxa2xx_spi_dma_handler()
264 /* finish this transfer, start the next */ pxa2xx_spi_dma_transfer()
324 /* Enable dma end irqs on SSP to detect end of transfer */ pxa2xx_spi_dma_prepare()
H A Dspi-au1550.c165 * setup dma channels from scratch on each spi transfer, based on bits_per_word
283 * no reliable way how to recognize that spi transfer is done
284 * dma complete callbacks are called before real spi transfer is finished
397 /* start the transfer */ au1550_spi_dma_txrxb()
439 * due to an spi error we consider transfer as done, au1550_spi_dma_irq_callback()
440 * so mask all events until before next transfer start au1550_spi_dma_irq_callback()
457 "dma transfer: receive FIFO overflow!\n"); au1550_spi_dma_irq_callback()
460 "dma transfer: unexpected SPI error " au1550_spi_dma_irq_callback()
468 /* transfer completed successfully */ au1550_spi_dma_irq_callback()
547 /* start the transfer */ au1550_spi_pio_txrxb()
574 * due to an error we consider transfer as done, au1550_spi_pio_irq_callback()
575 * so mask all events until before next transfer start au1550_spi_pio_irq_callback()
580 "pio transfer: unexpected SPI error " au1550_spi_pio_irq_callback()
627 * By simply restarting the spi transfer on Tx Underflow Error, au1550_spi_pio_irq_callback()
628 * we assume that spi transfer was paused instead of zeroes au1550_spi_pio_irq_callback()
639 /* transfer completed successfully */ au1550_spi_pio_irq_callback()
H A Dspi-dw-mid.c136 * dws->dma_chan_busy is set before the dma transfer starts, callback for tx
182 * dws->dma_chan_busy is set before the dma transfer starts, callback for rx
252 /* Prepare the TX dma transfer */ mid_spi_dma_transfer()
255 /* Prepare the RX dma transfer */ mid_spi_dma_transfer()
H A Dspi-mxs.c88 * ssp->clk_rate. Otherwise we would set the rate every transfer mxs_spi_setup_transfer()
208 /* Queue the DMA data transfer. */ mxs_spi_txrx_dma()
210 /* Prepare the transfer descriptor. */ mxs_spi_txrx_dma()
248 /* Queue the PIO register write transfer. */ mxs_spi_txrx_dma()
281 /* Start the transfer. */ mxs_spi_txrx_dma()
287 dev_err(ssp->dev, "DMA transfer timeout\n"); mxs_spi_txrx_dma()
390 /* De-assert on last transfer, inverted by cs_change flag */ mxs_spi_transfer_one()
H A Dspi-st-ssc4.c153 /* Setup transfer */ spi_st_transfer_one()
167 * If transfer is even-length, and 8 bits-per-word, then spi_st_transfer_one()
168 * implement as half-length 16 bits-per-word transfer spi_st_transfer_one()
186 /* Start transfer by writing to the TX FIFO */ spi_st_transfer_one()
190 /* Wait for transfer to complete */ spi_st_transfer_one()
H A Dspi-sun4i.c177 /* We don't support transfer larger than the FIFO */ sun4i_spi_transfer_one()
197 * Setup the transfer control register: Chip Select, sun4i_spi_transfer_one()
217 * If it's a TX only transfer, we don't want to fill the RX sun4i_spi_transfer_one()
264 /* Setup the transfer now... */ sun4i_spi_transfer_one()
278 /* Start the transfer */ sun4i_spi_transfer_one()
H A Dspi-sun6i.c167 /* We don't support transfer larger than the FIFO */ sun6i_spi_transfer_one()
184 * Setup the transfer control register: Chip Select, sun6i_spi_transfer_one()
205 * If it's a TX only transfer, we don't want to fill the RX sun6i_spi_transfer_one()
252 /* Setup the transfer now... */ sun6i_spi_transfer_one()
268 /* Start the transfer */ sun6i_spi_transfer_one()
H A Dspi.c694 "SPI transfer failed: %d\n", ret); spi_transfer_one_message()
709 "SPI transfer timed out\n"); spi_transfer_one_message()
715 "Bufferless transfer has length %u\n", spi_transfer_one_message()
757 * spi_finalize_current_transfer - report completion of a transfer
762 * transfer has finished and the next one may be scheduled.
777 * and transfer each message.
831 "failed to unprepare transfer hardware\n"); __spi_pump_messages()
871 "failed to prepare transfer hardware\n"); __spi_pump_messages()
903 "failed to transfer one message from queue\n"); __spi_pump_messages()
939 * message pump with high (realtime) priority to reduce the transfer spi_init_queue()
940 * latency on the bus by minimising the delay between a transfer spi_init_queue()
1120 * spi_queued_transfer - transfer function for queued transfers
1121 * @spi: spi device which is requesting transfer
1133 master->transfer = spi_queued_transfer; spi_master_initialize_queue()
1568 if (master->transfer) spi_register_master()
1737 * SPI protocol drivers may need to update the transfer mode if the
1840 * Set transfer bits_per_word and max speed as spi device default if __spi_validate()
1841 * it is not set for this transfer. __spi_validate()
1842 * Set transfer tx_nbits and rx_nbits as single transfer default __spi_validate()
1843 * (SPI_NBITS_SINGLE) if it is not set for this transfer. __spi_validate()
1867 * SPI transfer length should be multiple of SPI word size __spi_validate()
1889 /* check transfer tx/rx_nbits: __spi_validate()
1905 /* check transfer rx_nbits */ __spi_validate()
1933 return master->transfer(spi, message); __spi_async()
1937 * spi_async - asynchronous SPI transfer
1949 * callback returns, the driver which issued the transfer request may
1958 * On detection of any fault during the transfer, processing of
1962 * (This rule applies equally to all the synchronous transfer calls,
2001 * callback returns, the driver which issued the transfer request may
2010 * On detection of any fault during the transfer, processing of
2014 * (This rule applies equally to all the synchronous transfer calls,
2070 /* If we're not using the legacy transfer method then we will __spi_sync()
2071 * try to transfer in the calling context so special case. __spi_sync()
2075 if (master->transfer == spi_queued_transfer) { __spi_sync()
2094 if (master->transfer == spi_queued_transfer) __spi_sync()
2163 * exclusive access is over. Data transfer must be done by spi_sync_locked
2228 * Performance-sensitive or bulk transfer code should instead use
2245 * using the pre-allocated buffer or the transfer is too large. spi_write_then_read()
H A Dspi-pl022.c362 * message, so we left it active after the previous transfer, and it's
373 * @sgt_rx: scattertable for the RX transfer
374 * @sgt_tx: scattertable for the TX transfer
387 /* Message per-transfer pump */
782 * next_transfer - Move to the Next transfer in the current spi message
787 * message i.e whether its last transfer is done(STATE_DONE) or
788 * Next transfer is ready(STATE_RUNNING)
795 /* Move to next transfer */ next_transfer()
874 /* Move to next transfer */ dma_callback()
930 * configure_dma - configures the channels for the next transfer
1049 dev_dbg(&pl022->adev->dev, "using %d pages for transfer\n", pages); configure_dma()
1093 /* Put the callback on the RX transfer only, that should finish last */ configure_dma()
1246 * This function handles interrupts generated for an interrupt based transfer.
1252 * the transfer we move to the next transfer and schedule the tasklet.
1333 /* Move to next transfer */ pl022_interrupt_handler()
1347 struct spi_transfer *transfer) set_up_next_transfer()
1362 pl022->tx = (void *)transfer->tx_buf; set_up_next_transfer()
1364 pl022->rx = (void *)transfer->rx_buf; set_up_next_transfer()
1373 * pump_transfers - Tasklet function which schedules next transfer
1374 * when running in interrupt or DMA transfer mode.
1382 struct spi_transfer *transfer = NULL; pump_transfers() local
1387 transfer = pl022->cur_transfer; pump_transfers()
1403 /* Delay if requested at end of transfer before CS change */ pump_transfers()
1405 previous = list_entry(transfer->transfer_list.prev, pump_transfers()
1423 if (set_up_next_transfer(pl022, transfer)) { pump_transfers()
1467 /* Configure DMA transfer */ do_interrupt_dma_transfer()
1486 struct spi_transfer *transfer = NULL; do_polling_transfer() local
1498 transfer = pl022->cur_transfer; do_polling_transfer()
1500 /* Delay if requested at end of transfer */ do_polling_transfer()
1503 list_entry(transfer->transfer_list.prev, do_polling_transfer()
1517 if (set_up_next_transfer(pl022, transfer)) { do_polling_transfer()
1527 dev_dbg(&pl022->adev->dev, "polling transfer ongoing ...\n"); do_polling_transfer()
1546 /* Move to next transfer */ do_polling_transfer()
1819 * controller hardware here, that is not done until the actual transfer
2221 /* Initialize transfer pump */ pl022_probe()
1346 set_up_next_transfer(struct pl022 *pl022, struct spi_transfer *transfer) set_up_next_transfer() argument
/linux-4.1.27/drivers/net/wireless/rt2x00/
H A Drt2x00crypto.c163 unsigned int transfer = 0; rt2x00crypto_rx_insert_iv() local
205 memmove(skb->data + transfer, rt2x00crypto_rx_insert_iv()
206 skb->data + transfer + (iv_len - align), rt2x00crypto_rx_insert_iv()
208 transfer += header_length; rt2x00crypto_rx_insert_iv()
217 memmove(skb->data + transfer, rt2x00crypto_rx_insert_iv()
218 skb->data + transfer + iv_len + align, rt2x00crypto_rx_insert_iv()
220 transfer += header_length; rt2x00crypto_rx_insert_iv()
224 memcpy(skb->data + transfer, rxdesc->iv, iv_len); rt2x00crypto_rx_insert_iv()
225 transfer += iv_len; rt2x00crypto_rx_insert_iv()
232 memmove(skb->data + transfer, rt2x00crypto_rx_insert_iv()
233 skb->data + transfer + align, rt2x00crypto_rx_insert_iv()
242 transfer += payload_len; rt2x00crypto_rx_insert_iv()
250 memcpy(skb->data + transfer, &rxdesc->icv, 4); rt2x00crypto_rx_insert_iv()
251 transfer += icv_len; rt2x00crypto_rx_insert_iv()
254 rxdesc->size = transfer; rt2x00crypto_rx_insert_iv()
/linux-4.1.27/drivers/dma/
H A Dcoh901318.h29 * @src_addr: transfer source address
30 * @dst_addr: transfer destination address
88 * @size: transfer size
101 * coh901318_lli_fill_single() - Prepares the lli:s for dma single transfer
104 * @buf: transfer buffer
105 * @size: transfer size
109 * @dir: direction of transfer (to or from device)
120 * coh901318_lli_fill_single() - Prepares the lli:s for dma scatter list transfer
129 * @dir: direction of transfer (to or from device)
H A Dat_hdmac_regs.h29 #define AT_DMA_SSREQ(x) (0x1 << ((x) << 1)) /* Request a source single transfer on channel x */
30 #define AT_DMA_DSREQ(x) (0x1 << (1 + ((x) << 1))) /* Request a destination single transfer on channel x */
33 #define AT_DMA_SCREQ(x) (0x1 << ((x) << 1)) /* Request a source chunk transfer on channel x */
34 #define AT_DMA_DCREQ(x) (0x1 << (1 + ((x) << 1))) /* Request a destination chunk transfer on channel x */
43 /* Error, Chained Buffer transfer completed and Buffer transfer completed Interrupt registers */
185 * @tx_width: transfer width
388 /* enable interrupts on buffer transfer completion & error */ atc_setup_irq()
438 * set_desc_eol - set end-of-link to descriptor so it will end transfer
H A Dfsldma.c167 * EOTIE - End-of-transfer interrupt enable dma_init()
221 * the current transfer. On 83xx, this bit is the transfer error dma_halt()
248 * fsl_chan_set_src_loop_size - Set source address hold transfer size
252 * The set source address hold transfer size. The source
253 * address hold or loop transfer size is when the DMA transfer
280 * fsl_chan_set_dst_loop_size - Set destination address hold transfer size
284 * The set destination address hold transfer size. The destination
285 * address hold or loop transfer size is when the DMA transfer
314 * @size : Number of bytes to transfer in a single request
317 * The DMA request count is how many bytes are allowed to transfer before
342 * to set the number of bytes to transfer before pausing the channel.
359 * transfer immediately. The DMA channel will wait for the
565 * fsl_chan_xfer_ld_queue - transfer any pending transactions
609 * automatically at the end of a transfer. Therefore we must clear fsl_chan_xfer_ld_queue()
610 * it in software before starting the transfer. fsl_chan_xfer_ld_queue()
1053 * The DMA_INTERRUPT async_tx is a NULL transfer, which will fsldma_chan_irq()
1065 * and start the next transfer if it exist. fsldma_chan_irq()
1073 * If it current transfer is the end-of-transfer, fsldma_chan_irq()
1075 * prepare next transfer. fsldma_chan_irq()
H A Damba-pl08x.c39 * - separate CH_CONTROL2 register for transfer size,
40 * - bigger maximum transfer size,
44 * Memory to peripheral transfer may be visualized as
62 * - DMAC flow control: the transfer size defines the number of transfers
69 * - Peripheral flow control: the transfer size is ignored (and should be
71 * after the final transfer signalled by LBREQ or LSREQ. The DMAC
113 * LLI word for transfer size.
126 * busses for a transfer
128 * @maxwidth: the maximum width of a transfer on this bus
161 * @len: transfer len in bytes
204 * channel and is running a transfer on it
206 * channel, but the transfer is currently paused
291 * Number of LLIs in each LLI buffer allocated for one transfer
392 * and start the transfer.
468 * an on-going transfer, but as a method of shutting down a channel
469 * (eg, when it's no longer used) or terminating a transfer.
549 /* First get the remaining bytes in the active transfer */ pl08x_getbytes_chan()
596 * Try to locate a physical channel to be used for this transfer. If all
693 /* Find a waiting virtual channel for the next transfer. */ pl08x_phy_free()
762 /* Remove all src, dst and transfer size bits */ pl08x_cctl_bits()
812 * Autoselect a master bus to use for the transfer. Slave will be the chosen as
814 * masters address with width requirements of transfer (by sending few byte by
841 * Fills in one LLI for a certain transfer descriptor and advance the counter
922 * This fills in the table of LLIs for the transfer descriptor
994 * and after the transfer it will receive the last burst pl08x_fill_llis_for_desc()
995 * request from peripheral and so transfer finishes. pl08x_fill_llis_for_desc()
999 * transfer gets over, it can't load next lli. So in this pl08x_fill_llis_for_desc()
1089 * Calculate actual transfer size in relation to pl08x_fill_llis_for_desc()
1539 "unable to mux for transfer on %s due to platform restrictions\n", pl08x_init_txd()
H A Dtxx9dmac.h20 * be configured for memory-memory or device-memory transfer, but only
21 * one channel can do alignment-free memory-memory transfer at a time
26 * make one dedicated channel for memory-memory transfer. The
28 * for slave transfer. Some devices in the SoC are wired to certain
H A Ddma-jz4780.c94 * @dtc: transfer count (number of blocks of the transfer size specified in DCM
95 * to transfer) in the low 24 bits, offset of the next descriptor from the
97 * @sd: target/source stride difference (in stride transfer mode).
268 * This calculates the maximum transfer size that can be used with the jz4780_dma_setup_hwdesc()
270 * must be aligned to the transfer size, the total length must be jz4780_dma_setup_hwdesc()
271 * divisible by the transfer size, and we must not use more than the jz4780_dma_setup_hwdesc()
452 * There is an existing transfer, therefore this must be one jz4780_dma_begin()
495 /* Clear the DMA status and stop the transfer. */ jz4780_dma_terminate_all()
612 "channel IRQ with no active transfer\n"); jz4780_dma_chan_irq()
/linux-4.1.27/arch/mn10300/proc-mn2ws0050/include/proc/
H A Ddmactl-regs.h20 #define DMxCTR_BG 0x0000001f /* transfer request source */
45 #define DMxCTR_SAM 0x00000060 /* DMA transfer src addr mode */
49 #define DMxCTR_DAM 0x00000300 /* DMA transfer dest addr mode */
53 #define DMxCTR_UT 0x00006000 /* DMA transfer unit */
59 #define DMxCTR_TEN 0x00010000 /* DMA channel transfer enable */
65 #define DMxCTR_RQF 0x01000000 /* DMA transfer request flag */
66 #define DMxCTR_PERR 0x40000000 /* DMA transfer parameter error flag */
67 #define DMxCTR_XEND 0x80000000 /* DMA transfer end flag */
74 #define DMxSIZ_CT 0x000fffff /* number of bytes to transfer */
/linux-4.1.27/drivers/media/usb/dvb-usb-v2/
H A Dmxl111sf.h74 /* use usb alt setting 1 for EP4 ISOC transfer (dvb-t),
75 EP5 BULK transfer (atsc-mh),
76 EP6 BULK transfer (atsc/qam),
77 use usb alt setting 2 for EP4 BULK transfer (dvb-t),
78 EP5 ISOC transfer (atsc-mh),
79 EP6 ISOC transfer (atsc/qam),
/linux-4.1.27/arch/mn10300/include/asm/
H A Ddma.h60 /* Set only the page register bits of the transfer address.
70 /* Set transfer address & page bits for specific DMA channel.
78 /* Set transfer size (max 64k for DMA1..3, 128k for DMA5..7) for
91 /* Get DMA residue count. After a DMA transfer, this
92 * should return zero. Reading this while a DMA transfer is
95 * Otherwise, it returns the number of _bytes_ left to transfer.
/linux-4.1.27/arch/ia64/sn/kernel/
H A Dbte.c64 * Use the block transfer engine to move kernel memory from src to dest
68 * src - physical address of the transfer source.
69 * dest - physical address of the transfer destination.
70 * len - number of bytes to transfer from source to dest.
185 /* Calculate the number of cache lines to transfer. */ bte_copy()
202 /* Initiate the transfer */ bte_copy()
249 * use the block transfer engine to move kernel
253 * src - physical address of the transfer source.
254 * dest - physical address of the transfer destination.
255 * len - number of bytes to transfer from source to dest.
292 * At this point, the transfer is broken into bte_unaligned_copy()
308 * we make the first section be the entire transfer bte_unaligned_copy()
316 * use the bte to transfer the bulk of the bte_unaligned_copy()
365 /* now transfer the middle. */ bte_unaligned_copy()
380 * The transfer is not symmetric, we will bte_unaligned_copy()
429 * Indicate that all the block transfer engines on this node bte_init_node()
457 * so the first transfer can occur. bte_init_node()
/linux-4.1.27/drivers/usb/image/
H A Dmicrotek.c77 * 20000515 Put transfer context and URB in mts_desc (john)
190 MTS_DEBUG("transfer = 0x%x context = 0x%x\n",(int)transfer,(int)context ); \
191 MTS_DEBUG("status = 0x%x data-length = 0x%x sent = 0x%x\n",transfer->status,(int)context->data_length, (int)transfer->actual_length ); \
207 struct mts_transfer_context* context = (struct mts_transfer_context*)transfer->context; \
366 static void mts_transfer_cleanup( struct urb *transfer );
367 static void mts_do_sg(struct urb * transfer);
370 void mts_int_submit_urb (struct urb* transfer, mts_int_submit_urb() argument
377 /* Holding transfer->context->lock! */ mts_int_submit_urb()
383 usb_fill_bulk_urb(transfer, mts_int_submit_urb()
392 res = usb_submit_urb( transfer, GFP_ATOMIC ); mts_int_submit_urb()
396 mts_transfer_cleanup(transfer); mts_int_submit_urb()
401 static void mts_transfer_cleanup( struct urb *transfer ) mts_transfer_cleanup()
410 static void mts_transfer_done( struct urb *transfer ) mts_transfer_done()
417 mts_transfer_cleanup(transfer); mts_transfer_done()
421 static void mts_get_status( struct urb *transfer ) mts_get_status()
426 mts_int_submit_urb(transfer, mts_get_status()
434 static void mts_data_done( struct urb* transfer ) mts_data_done()
437 int status = transfer->status; mts_data_done()
440 if ( context->data_length != transfer->actual_length ) { mts_data_done()
442 transfer->actual_length); mts_data_done()
447 mts_get_status(transfer); mts_data_done()
451 static void mts_command_done( struct urb *transfer ) mts_command_done()
454 int status = transfer->status; mts_command_done()
468 mts_transfer_cleanup(transfer); mts_command_done()
474 mts_int_submit_urb(transfer, mts_command_done()
480 mts_int_submit_urb(transfer, mts_command_done()
487 mts_get_status(transfer); mts_command_done()
492 static void mts_do_sg (struct urb* transfer) mts_do_sg() argument
495 int status = transfer->status; mts_do_sg()
503 mts_transfer_cleanup(transfer); mts_do_sg()
508 mts_int_submit_urb(transfer, mts_do_sg()
/linux-4.1.27/include/linux/spi/
H A Dspi_bitbang.h15 * for this transfer; zeroes restore defaults from spi_device.
25 * already have one (transfer.{tx,rx}_dma is zero), or use PIO
H A Dspi.h39 * The spi_transfer.speed_hz can override this for each transfer.
45 * each word in a transfer (by specifying SPI_LSB_FIRST).
51 * The spi_transfer.bits_per_word can override this for each transfer.
232 * supported. If set, the SPI core will reject any transfer with an
235 * @min_speed_hz: Lowest supported transfer speed
236 * @max_speed_hz: Highest supported transfer speed
246 * @transfer: adds a message to the controller's transfer queue.
267 * @max_dma_len: Maximum length of a DMA transfer for the device.
269 * so the subsystem requests the driver to prepare the transfer hardware
271 * @transfer_one_message: the subsystem calls the driver to transfer a single
281 * @prepare_message: set up the controller to transfer a single message,
284 * @transfer_one: transfer a single spi_transfer.
285 * - return 0 if the transfer is finished,
286 * - return 1 if the transfer is still in progress. When
287 * the driver is finished with this transfer it must
289 * can issue the next transfer. Note: transfer_one and
347 /* limits on transfer speed */
376 * + The transfer() method may not sleep; its main role is
393 int (*transfer)(struct spi_device *spi, member in struct:spi_master
401 * exists and returns true then the transfer will be mapped
412 * master transfer queueing mechanism. If these are used, the
413 * transfer() function above must NOT be specified by the driver.
448 struct spi_transfer *transfer);
515 * The spi_messages themselves consist of a series of read+write transfer
538 * transfer. If 0 the default (from @spi_device) is used.
540 * for this transfer. If 0 the default (from @spi_device) is used.
541 * @cs_change: affects chipselect after this transfer completes
542 * @delay_usecs: microseconds to delay after this transfer before
544 * the next transfer or completing this @spi_message.
567 * When the word size of the SPI transfer is not a power-of-two multiple
573 * it stays selected until after the last transfer in a message. Drivers
576 * (i) If the transfer isn't the last one in the message, this flag is
582 * (ii) When the transfer is the last one in the message, the chip may
583 * stay selected until the next transfer. On multi-device SPI busses
592 * When SPI can transfer in 1x,2x or 4x. It can get this transfer information
594 * two should both be set. User can set transfer mode with SPI_NBITS_SINGLE(1x)
595 * SPI_NBITS_DUAL(2x) and SPI_NBITS_QUAD(4x) to support these three transfer.
621 #define SPI_NBITS_SINGLE 0x01 /* 1bit transfer */
622 #define SPI_NBITS_DUAL 0x02 /* 2bits transfer */
623 #define SPI_NBITS_QUAD 0x04 /* 4bits transfer */
633 * @transfers: list of transfer segments in this transaction
636 * addresses for each transfer buffer
650 * as single programmed DMA transfer. On all systems, these messages are
668 * last transfer ... allowing things like "read 16 bit length L"
765 /* All these synchronous SPI transfer routines are utilities layered
766 * over the core async transfer primitive. Here, "synchronous" means
767 * they will sleep uninterruptibly until the async transfer completes.
824 * spi_sync_transfer - synchronous SPI data transfer
830 * Does a synchronous SPI data transfer of the given spi_transfer array.
961 * as the default transfer wordsize) is not included here.
/linux-4.1.27/arch/arm/include/asm/
H A Ddma.h55 /* Set only the page register bits of the transfer address.
88 /* Test whether the specified channel has an active DMA transfer
118 /* Set the transfer direction for this channel
122 * DMA transfer direction immediately, but defer it to the
127 /* Set the transfer speed for this channel
131 /* Get DMA residue count. After a DMA transfer, this
132 * should return zero. Reading this while a DMA transfer is
135 * Otherwise, it returns the number of _bytes_ left to transfer.
H A Dcache.h14 * cache before the transfer is done, causing old data to be seen by
/linux-4.1.27/drivers/block/
H A Dloop.h35 int (*transfer)(struct loop_device *, int cmd, member in struct:loop_device
75 /* Support for loadable transfer modules */
78 int (*transfer)(struct loop_device *lo, int cmd, member in struct:loop_func_table
/linux-4.1.27/drivers/scsi/
H A Ddc395x.h287 #define SCSIXFERDONE 0x0800 /* SCSI SCSI transfer done */
288 #define SCSIXFERCNT_2_ZERO 0x0100 /* SCSI SCSI transfer count to zero */
310 #define DO_CLRFIFO 0x0004 /* Clear SCSI transfer FIFO */
356 /* transfer. */
362 /* are used to transfer data */
367 /* are used to transfer data */
450 #define SCMD_FIFO_OUT 0xC0 /* SCSI FIFO transfer out */
451 #define SCMD_DMA_OUT 0xC1 /* SCSI DMA transfer out */
452 #define SCMD_FIFO_IN 0xC2 /* SCSI FIFO transfer in */
453 #define SCMD_DMA_IN 0xC3 /* SCSI DMA transfer in */
470 /* 50 Initiator transfer information out sequence without ATN */
472 /* 70 Initiator transfer information out sequence with ATN */
474 /* 74 Initiator transfer information out sequence with ATN3 */
476 /* 52 Initiator transfer information in sequence without ATN */
478 /* 72 Initiator transfer information in sequence with ATN */
480 /* 76 Initiator transfer information in sequence with ATN3 */
482 /* 90 Initiator transfer information out command complete */
484 /* 92 Initiator transfer information in command complete */
538 #define STOPDMAXFER 0x08 /* Stop DMA transfer */
539 #define ABORTXFER 0x04 /* Abort DMA transfer */
540 #define CLRXFIFO 0x02 /* Clear DMA transfer FIFO */
541 #define STARTDMAXFER 0x01 /* Start DMA transfer */
549 #define FORCEDMACOMP 0x10 /* Force DMA transfer complete */
550 #define DMAXFERERROR 0x08 /* DMA transfer error */
551 #define DMAXFERABORT 0x04 /* DMA transfer abort */
556 #define EN_FORCEDMACOMP 0x10 /* Force DMA transfer complete */
557 #define EN_DMAXFERERROR 0x08 /* DMA transfer error */
558 #define EN_DMAXFERABORT 0x04 /* DMA transfer abort */
H A DNCR5380.h88 * transfer, causing the chip to hog the bus. You probably don't want
134 #define BASR_END_DMA_TRANSFER 0x80 /* ro set on end of transfer */
147 * Used in DMA transfer mode, data is latched from the SCSI bus on
165 #define CSR_TRANS_DIR 0x40 /* rw Data transfer direction */
166 #define CSR_SCSI_BUFF_INTR 0x20 /* rw Enable int on transfer ready */
182 /* Resume transfer after disconnect */
284 * transfer to handle chip overruns */
344 * @ptr: block to transfer (virtual address)
345 * @count: number of bytes to transfer
348 * Program the DMA controller ready to perform an ISA DMA transfer
374 panic("scsi%d : attempted unaligned DMA transfer\n", instance->host_no); NCR5380_pc_dma_setup()
391 * @ptr: block to transfer (virtual address)
392 * @count: number of bytes to transfer
408 * @ptr: block to transfer (virtual address)
409 * @count: number of bytes to transfer
H A Daha152x.h16 #define SXFRCTL0 (HOSTIOPORT0+0x01) /* SCSI transfer control 0 */
17 #define SXFRCTL1 (HOSTIOPORT0+0x02) /* SCSI transfer control 1 */
24 #define STCNT0 (HOSTIOPORT0+0x08) /* SCSI transfer count 0 */
25 #define STCNT1 (HOSTIOPORT0+0x09) /* SCSI transfer count 1 */
26 #define STCNT2 (HOSTIOPORT0+0x0a) /* SCSI transfer count 2 */
73 /* SCSI transfer control 0 */
81 /* SCSI transfer control 1 */
129 /* SCSI transfer count */
H A Dqlogicfas408.h36 advanced features if your device can transfer faster than 5Mb/sec.
52 /* This when set to 1 will set a faster sync transfer rate */
57 /* This is the sync transfer divisor, XTALFREQ/X will be the maximum
68 If this is 0, the bus will only transfer asynchronously */
H A Dgvp11.h23 * if the transfer address ANDed with this results in a non-zero
H A Daha1542.h83 /* Outbound data transfer, length is checked*/
84 /* Inbound data transfer, length is checked */
H A Desp_scsi.h10 #define ESP_TCLOW 0x00UL /* rw Low bits transfer count 0x00 */
11 #define ESP_TCMED 0x01UL /* rw Mid bits transfer count 0x04 */
173 #define ESP_STAT2_XCNT 0x04 /* The transfer counter is latched */
244 * input clock rates we try to do 10mb/s although I don't think a transfer can
386 /* Return the maximum allowable size of a DMA transfer for a
398 /* Drain any pending DMA in the DMA engine after a transfer.
403 /* Invalidate the DMA engine after a DMA transfer. */
406 /* Setup an ESP command that will use a DMA transfer.
407 * The 'esp_count' specifies what transfer length should be
408 * programmed into the ESP transfer counter registers, whereas
411 * is non-zero, this transfer is a write into memory. 'cmd'
H A Datari_scsi.c298 * that some other 5380 interrupt occurred within the DMA transfer. scsi_tt_intr()
330 * wrong and the next transfer will start behind where scsi_tt_intr()
333 * multiple and the originally expected transfer size scsi_tt_intr()
385 * other 5380 interrupt that finishes the DMA transfer. We have to scsi_falcon_intr()
607 /* On writes, round up the transfer length to the next multiple of 512 atari_scsi_dma_setup()
642 * needed here: The transfer is block-mode only if the 'fixed' bit is falcon_classify_cmd()
668 /* TT SCSI DMA can transfer arbitrary #bytes */ atari_dma_xfer_len()
676 * case, the given transfer length is an "allocation length". Now it atari_dma_xfer_len()
689 * the transfer (allocation) length is < 1024, hoping that no cmd. not atari_dma_xfer_len()
692 * unproblematic anyways, since the targets aborts the transfer after atari_dma_xfer_len()
695 * Another point: If the transfer is from/to an non-ST-RAM address, we atari_dma_xfer_len()
700 /* Write operation can always use the DMA, but the transfer size must atari_dma_xfer_len()
706 /* Read operations: if the wanted transfer length is not a multiple of atari_dma_xfer_len()
724 /* For unknown commands assume block transfers if the transfer atari_dma_xfer_len()
739 dprintk(NDEBUG_DMA, "Sorry, must cut DMA transfer size to %ld bytes " atari_dma_xfer_len()
789 /* Abort a maybe active DMA transfer */ atari_scsi_bus_reset()
H A Da2091.h23 * if the transfer address ANDed with this results in a non-zero
H A Da3000.h23 * if the transfer address ANDed with this results in a non-zero
/linux-4.1.27/include/uapi/linux/spi/
H A Dspidev.h57 * struct spi_ioc_transfer - describes a single SPI transfer
64 * @delay_usecs: If nonzero, how long to delay after the last bit transfer
65 * before optionally deselecting the device before the next transfer.
66 * @cs_change: True to deselect device before starting the next transfer.
77 * Each transfer may be half duplex (either direction) or full duplex.
83 * So for example one transfer might send a nine bit command (right aligned
87 * last transfer might write some register values.
/linux-4.1.27/drivers/mmc/core/
H A Dsdio_io.c147 * data transfer use the optimal (least) number of commands.
187 * Calculate the maximum byte mode transfer size
205 * sdio_align_size - pads a transfer size to a more optimal value
207 * @sz: original transfer size
234 * If we can still do this with just a byte transfer, then sdio_align_size()
242 * Check if the transfer is already block aligned sdio_align_size()
301 /* Split an arbitrarily sized data transfer into several
310 /* Do the bulk of the transfer using block mode (if supported). */ sdio_io_rw_ext_helper()
312 /* Blocks per command is limited by host count, host transfer sdio_io_rw_ext_helper()
359 * @err_ret: optional status value from transfer
391 * @err_ret: optional status value from transfer
395 * transfer.
414 * @err_ret: optional status value from transfer
447 * value indicates if the transfer succeeded or not.
464 * value indicates if the transfer succeeded or not.
481 * value indicates if the transfer succeeded or not.
498 * value indicates if the transfer succeeded or not.
511 * @err_ret: optional status value from transfer
540 * @err_ret: optional status value from transfer
544 * transfer.
562 * @err_ret: optional status value from transfer
592 * @err_ret: optional status value from transfer
596 * transfer.
614 * @err_ret: optional status value from transfer
647 * @err_ret: optional status value from transfer
650 * @err_ret will contain the status of the actual transfer.
/linux-4.1.27/arch/frv/include/asm/
H A Dmb93493-regs.h104 #define MB93493_VCC_RDTS 0x128 /* DMA transfer size */
105 #define MB93493_VCC_RDTS_4B 0x01000000 /* 4-byte transfer */
106 #define MB93493_VCC_RDTS_32B 0x03000000 /* 32-byte transfer */
200 #define I2S_AISTR_OTST 0x00000003 /* status of output data transfer */
201 #define I2S_AISTR_OTR 0x00000010 /* output transfer request pending */
204 #define I2S_AISTR_ODS 0x00000100 /* output DMA transfer size */
205 #define I2S_AISTR_ODE 0x00000400 /* output DMA transfer request enable */
206 #define I2S_AISTR_OTRIE 0x00001000 /* output transfer request interrupt enable */
210 #define I2S_AISTR_ITST 0x00030000 /* status of input data transfer */
212 #define I2S_AISTR_ITR 0x00100000 /* input transfer request pending */
215 #define I2S_AISTR_IDS 0x01000000 /* input DMA transfer size */
216 #define I2S_AISTR_IDE 0x04000000 /* input DMA transfer request enable */
217 #define I2S_AISTR_ITRIE 0x10000000 /* input transfer request interrupt enable */
/linux-4.1.27/drivers/i2c/busses/
H A Di2c-mxs.c191 /* Queue the PIO register write transfer. */ mxs_i2c_dma_setup_xfer()
202 /* Queue the DMA data transfer. */ mxs_i2c_dma_setup_xfer()
218 /* Queue the PIO register write transfer. */ mxs_i2c_dma_setup_xfer()
230 /* Queue the DMA data transfer. */ mxs_i2c_dma_setup_xfer()
249 /* Queue the PIO register write transfer. */ mxs_i2c_dma_setup_xfer()
261 /* Queue the DMA data transfer. */ mxs_i2c_dma_setup_xfer()
283 /* Start the transfer. */ mxs_i2c_dma_setup_xfer()
388 * to support PIO, when we try to transfer any amount of data mxs_i2c_pio_setup_xfer()
391 * transfer. This in turn will mess up the next transfer as mxs_i2c_pio_setup_xfer()
401 * PIO READ transfer: mxs_i2c_pio_setup_xfer()
403 * This transfer MUST be limited to 4 bytes maximum. It is not mxs_i2c_pio_setup_xfer()
404 * possible to transfer more than four bytes via PIO, since we mxs_i2c_pio_setup_xfer()
446 * PIO WRITE transfer: mxs_i2c_pio_setup_xfer()
450 * fast enough. It is possible to transfer arbitrary amount mxs_i2c_pio_setup_xfer()
463 /* Start the transfer with START condition. */ mxs_i2c_pio_setup_xfer()
466 /* If the transfer is long, use clock stretching. */ mxs_i2c_pio_setup_xfer()
476 /* This is the last transfer of the message. */ mxs_i2c_pio_setup_xfer()
494 * Compute the size of the transfer and shift the mxs_i2c_pio_setup_xfer()
528 /* Wait for the end of the transfer. */ mxs_i2c_pio_setup_xfer()
582 * The MX28 I2C IP block can only do PIO READ for transfer of to up mxs_i2c_xfer_msg()
583 * 4 bytes of length. The write transfer is not limited as it can use mxs_i2c_xfer_msg()
613 * If the transfer fails with a NAK from the slave the mxs_i2c_xfer_msg()
629 * reset the block after every transfer to play safe. mxs_i2c_xfer_msg()
H A Di2c-cbus-gpio.c63 * @len: size of the transfer
122 /* We don't want interrupts disturbing our transfer */ cbus_transfer()
125 /* Reset state and start of transfer, SEL stays down during transfer */ cbus_transfer()
158 /* Indicate end of transfer, SEL goes up until next transfer */ cbus_transfer()
H A Di2c-meson.c70 * @last: Flag set for the last message in the transfer
71 * @count: Number of bytes to be sent/received in current transfer
75 * @done: Completion used to wait for transfer termination
329 /* Start the transfer */ meson_i2c_xfer_msg()
337 * handlers triggered by a transfer terminated after the meson_i2c_xfer_msg()
449 * A transfer is triggered when START bit changes from 0 to 1. meson_i2c_probe()
H A Di2c-bfin-twi.c128 /* Faulty slave devices, may drive SDA low after a transfer bfin_twi_handle_interrupt()
149 /* If it is a quick transfer, only address without data, bfin_twi_handle_interrupt()
256 * One i2c master transfer
331 dev_err(&adap->dev, "master transfer timeout\n"); bfin_twi_do_master_xfer()
344 * Generic i2c master transfer entrypoint
353 * One I2C SMBus transfer
535 dev_err(&adap->dev, "smbus transfer timeout\n"); bfin_twi_do_smbus_xfer()
545 * Generic I2C SMBus transfer entrypoint
H A Di2c-cadence.c37 /* Read or Write Master transfer 0 = Transmitter, 1 = Receiver */
53 * bits. A write access to this register always initiates a transfer if the I2C
131 * @curr_recv_count: Number of bytes to be received in current transfer
180 * This function handles the data interrupt, transfer complete interrupt and
204 * Check if transfer size register needs to be updated again for a cdns_i2c_isr()
238 * The controller sends NACK to the slave when transfer size cdns_i2c_isr()
241 * maintain transfer size non-zero while performing a large cdns_i2c_isr()
253 * transfer size and update register accordingly. cdns_i2c_isr()
279 /* When sending, handle transfer complete interrupt */ cdns_i2c_isr()
360 * max transfer size. Set transfer size register with no of bytes cdns_i2c_mrecv()
361 * receive if it is less than transfer size and transfer size if cdns_i2c_mrecv()
523 * cdns_i2c_master_xfer - The main i2c transfer function
526 * @num: the number of messages to transfer
528 * Initiates the send/recv activity based on the transfer message received.
H A Di2c-ibm_iic.c157 /* Clear transfer count */ iic_dev_init()
342 * Get master transfer result and clear errors if any.
376 * Try to abort active transfer.
406 * Wait for master transfer to complete.
458 * Low level master transfer routine
488 /* Start transfer */ iic_xfer_bytes()
517 * Set target slave address for master transfer
551 * Generic master transfer entrypoint.
597 * We *cannot* have unfinished previous transfer iic_xfer()
619 /* Do real transfer */ iic_xfer()
H A Di2c-tegra.c104 * msg_end_type: The bus control which need to be send at end of transfer.
105 * @MSG_END_STOP: Send stop pulse at end of transfer.
106 * @MSG_END_REPEAT_START: Send repeat start at end of transfer.
118 * @has_continue_xfer_support: Continue transfer supports.
119 * @has_per_pkt_xfer_complete_irq: Has enable/disable capability for transfer
147 * @irq: irq number of transfer complete interrupt
149 * @msg_complete: transfer completion notifier
593 dev_err(i2c_dev->dev, "i2c transfer timed out\n"); tegra_i2c_xfer_msg()
599 dev_dbg(i2c_dev->dev, "transfer complete: %lu %d %d\n", tegra_i2c_xfer_msg()
/linux-4.1.27/drivers/staging/iio/frequency/
H A Dad9834.h45 * @xfer: default spi transfer
47 * @freq_xfer: tuning word spi transfer
66 * transfer buffers to live in their own cache lines.
H A Dad9832.h66 * @xfer: default spi transfer
68 * @freq_xfer: tuning word spi transfer
70 * @phase_xfer: tuning word spi transfer
92 * transfer buffers to live in their own cache lines.
/linux-4.1.27/drivers/dma/hsu/
H A Dhsu.h25 #define HSU_CH_MTSR 0x14 /* minimum transfer size */
27 #define HSU_CH_DxTSR(x) (0x24 + 8 * (x)) /* desc transfer size */
29 #define HSU_CH_D0TSR 0x24 /* desc 0 transfer size */
/linux-4.1.27/include/uapi/linux/
H A Dpg.h26 may transfer at most PG_MAX_DATA bytes. Note that the driver must
47 int dlen; /* number of bytes expected to transfer */
57 int dlen; /* size of device transfer request */
H A Dbsg.h37 __u32 dout_iovec_count; /* [i] 0 -> "flat" dout transfer else
40 __u32 din_iovec_count; /* [i] 0 -> "flat" din transfer */
H A Dchio.h9 #define CHET_DT 3 /* data transfer element (tape/cdrom/whatever) */
33 int cp_ndrives; /* number of data transfer elements (CHET_DT) */
120 int cge_id; /* scsi id (for data transfer elements) */
121 int cge_lun; /* scsi lun (for data transfer elements) */
H A Di2c-dev.h49 #define I2C_RDWR 0x0707 /* Combined R/W transfer (one STOP only) */
52 #define I2C_SMBUS 0x0720 /* SMBus transfer */
/linux-4.1.27/arch/arm/plat-pxa/include/plat/
H A Ddma.h61 volatile u32 dsadr; /* DSADR value for the current transfer */
62 volatile u32 dtadr; /* DTADR value for the current transfer */
63 volatile u32 dcmd; /* DCMD value for the current transfer */
/linux-4.1.27/drivers/mtd/devices/
H A Dsst25l.c217 struct spi_transfer transfer[2]; sst25l_read() local
223 memset(&transfer, 0, sizeof(transfer)); sst25l_read()
230 transfer[0].tx_buf = command; sst25l_read()
231 transfer[0].len = sizeof(command); sst25l_read()
232 spi_message_add_tail(&transfer[0], &message); sst25l_read()
234 transfer[1].rx_buf = buf; sst25l_read()
235 transfer[1].len = len; sst25l_read()
236 spi_message_add_tail(&transfer[1], &message); sst25l_read()
/linux-4.1.27/arch/unicore32/include/asm/
H A Dcache.h22 * cache before the transfer is done, causing old data to be seen by
/linux-4.1.27/drivers/usb/host/whci/
H A Dwhci-hc.h34 * QTD_MAX_TXFER_SIZE - max number of bytes to transfer with a single
45 * This describes the data for a bulk, control or interrupt transfer.
50 __le32 status; /*< remaining transfer len and transfer status */
57 #define QTD_STS_HALTED (1 << 30) /* transfer halted */
65 #define QTD_STS_LEN(l) ((l) << 0) /* transfer length */
75 * transfer.
83 __le32 options; /*< misc transfer options */
155 #define QH_INFO1_DIR_IN (1 << 4) /* IN transfer */
156 #define QH_INFO1_DIR_OUT (0 << 4) /* OUT transfer */
157 #define QH_INFO1_TR_TYPE_CTRL (0x0 << 5) /* control transfer */
158 #define QH_INFO1_TR_TYPE_ISOC (0x1 << 5) /* isochronous transfer */
159 #define QH_INFO1_TR_TYPE_BULK (0x2 << 5) /* bulk transfer */
163 #define QH_INFO1_SET_INACTIVE (1 << 15) /* set inactive after transfer */
184 * usb_pipe_to_qh_type - USB core pipe type to QH transfer type
224 * Each TD may refer to at most 1 MiB of data. If a single transfer
/linux-4.1.27/fs/ntfs/
H A Dmst.c2 * mst.c - NTFS multi sector transfer protection handling code. Part of the
26 * post_read_mst_fixup - deprotect multi sector transfer protected data
30 * Perform the necessary post read multi sector transfer fixup and detect the
72 * Check for incomplete multi sector transfer(s). post_read_mst_fixup()
77 * Incomplete multi sector transfer detected! )-: post_read_mst_fixup()
103 * pre_write_mst_fixup - apply multi sector transfer protection
107 * Perform the necessary pre write multi sector transfer fixup on the data
172 * post_write_mst_fixup - fast deprotect multi sector transfer protected data
175 * Perform the necessary post write multi sector transfer fixup, not checking
/linux-4.1.27/include/linux/platform_data/
H A Data-samsung_cf.h18 * transfer in true-ide mode.
H A Dedma.h19 * Slot Each PaRAM slot holds a DMA transfer descriptor (PaRAM
21 * next PaRAM slot (if any), options for the transfer, and
26 * buffer or for several discontiguous smaller buffers. An EDMA transfer
29 * transfer completes, the "link" field may be used to reload the channel's
30 * PaRAM slot with a new transfer descriptor.
H A Ds3c-hsudc.h9 * can be configured for Bulk or Interrupt transfer mode.
H A Dvideo_s3c.h29 * @setup_gpio: Setup the external GPIO pins to the right state to transfer
/linux-4.1.27/arch/powerpc/include/asm/
H A Ddbdma.h45 __le16 req_count; /* requested byte transfer count */
50 __le16 xfer_status; /* transfer status */
54 #define OUTPUT_MORE 0 /* transfer memory data to stream */
56 #define INPUT_MORE 0x2000 /* transfer stream data to memory */
H A Ddma.h28 /* The maximum address that we can perform a DMA transfer to on this platform */
46 * - ALL registers are 8 bits only, regardless of transfer size
51 * - transfer count loaded to registers is 1 less than actual count
78 * Again, channels 5-7 transfer _physical_ words (16 bits), so addresses
229 /* Set only the page register bits of the transfer address.
268 /* Set transfer address & page bits for specific DMA channel.
288 /* Set transfer size (max 64k for DMA1..3, 128k for DMA5..7) for
313 /* Get DMA residue count. After a DMA transfer, this
314 * should return zero. Reading this while a DMA transfer is
317 * Otherwise, it returns the number of _bytes_ left to transfer.
H A Dsmu.h115 * 1: transfer type/format (see below)
125 * The transfer types are the same good old Apple ones it seems,
127 * - 0x00: Simple transfer
128 * - 0x01: Subaddress transfer (addr write + data tx, no restart)
129 * - 0x02: Combined transfer (addr write + restart + data tx)
133 * At this point, the OF driver seems to have a limitation on transfer
167 /* transfer types */
296 * transfer blocks of data from the SMU. So far, I've decrypted it's
298 * break your transfer in "chunks" since that command cannot transfer
310 * byte 6: size to transfer (up to max chunk size)
491 u8 type; /* i2c transfer type */
496 u8 datalen; /* length of transfer */
/linux-4.1.27/sound/soc/samsung/
H A Ddma.h20 int dma_size; /* Size of the DMA transfer */
/linux-4.1.27/arch/blackfin/mach-bf548/include/mach/
H A DdefBF542.h28 #define ATAPI_PIO_TFRCNT 0xffc0382c /* ATAPI PIO mode transfer count */
29 #define ATAPI_DMA_TFRCNT 0xffc03830 /* ATAPI DMA mode transfer count */
30 #define ATAPI_UMAIN_TFRCNT 0xffc03834 /* ATAPI UDMAIN transfer count */
31 #define ATAPI_UDMAOUT_TFRCNT 0xffc03838 /* ATAPI UDMAOUT transfer count */
256 #define USB_DMA0COUNTLOW 0xffc04010 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
257 #define USB_DMA0COUNTHIGH 0xffc04014 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
264 #define USB_DMA1COUNTLOW 0xffc04030 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
265 #define USB_DMA1COUNTHIGH 0xffc04034 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
272 #define USB_DMA2COUNTLOW 0xffc04050 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
273 #define USB_DMA2COUNTHIGH 0xffc04054 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
280 #define USB_DMA3COUNTLOW 0xffc04070 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
281 #define USB_DMA3COUNTHIGH 0xffc04074 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
288 #define USB_DMA4COUNTLOW 0xffc04090 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
289 #define USB_DMA4COUNTHIGH 0xffc04094 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
296 #define USB_DMA5COUNTLOW 0xffc040b0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
297 #define USB_DMA5COUNTHIGH 0xffc040b4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
304 #define USB_DMA6COUNTLOW 0xffc040d0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
305 #define USB_DMA6COUNTHIGH 0xffc040d4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
312 #define USB_DMA7COUNTLOW 0xffc040f0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
313 #define USB_DMA7COUNTHIGH 0xffc040f4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
378 #define PIO_XFER_ON 0x1 /* PIO transfer in progress */
379 #define MULTI_XFER_ON 0x2 /* Multi-word DMA transfer in progress */
380 #define ULTRA_XFER_ON 0x4 /* Ultra DMA transfer in progress */
390 #define PIO_DONE_MASK 0x2 /* PIO transfer done interrupt mask */
391 #define MULTI_DONE_MASK 0x4 /* Multi-DMA transfer done interrupt mask */
392 #define UDMAIN_DONE_MASK 0x8 /* Ultra-DMA in transfer done interrupt mask */
393 #define UDMAOUT_DONE_MASK 0x10 /* Ultra-DMA out transfer done interrupt mask */
394 #define HOST_TERM_XFER_MASK 0x20 /* Host terminate current transfer interrupt mask */
395 #define MULTI_TERM_MASK 0x40 /* Device terminate Multi-DMA transfer interrupt mask */
396 #define UDMAIN_TERM_MASK 0x80 /* Device terminate Ultra-DMA-in transfer interrupt mask */
397 #define UDMAOUT_TERM_MASK 0x100 /* Device terminate Ultra-DMA-out transfer interrupt mask */
402 #define PIO_DONE_INT 0x2 /* PIO transfer done interrupt status */
403 #define MULTI_DONE_INT 0x4 /* Multi-DMA transfer done interrupt status */
404 #define UDMAIN_DONE_INT 0x8 /* Ultra-DMA in transfer done interrupt status */
405 #define UDMAOUT_DONE_INT 0x10 /* Ultra-DMA out transfer done interrupt status */
406 #define HOST_TERM_XFER_INT 0x20 /* Host terminate current transfer interrupt status */
407 #define MULTI_TERM_INT 0x40 /* Device terminate Multi-DMA transfer interrupt status */
408 #define UDMAIN_TERM_INT 0x80 /* Device terminate Ultra-DMA-in transfer interrupt status */
409 #define UDMAOUT_TERM_INT 0x100 /* Device terminate Ultra-DMA-out transfer interrupt status */
706 #define PROTOCOL_T 0xc /* transfer type */
715 #define PROTOCOL_R 0xc /* transfer type */
735 #define DIRECTION 0x2 /* direction of DMA transfer */
751 #define DMA_COUNT_HIGH 0xffff /* Upper 16-bits of byte count of DMA transfer for DMA master channel */
755 #define DMA_COUNT_LOW 0xffff /* Lower 16-bits of byte count of DMA transfer for DMA master channel */
H A DdefBF547.h136 #define ATAPI_PIO_TFRCNT 0xffc0382c /* ATAPI PIO mode transfer count */
137 #define ATAPI_DMA_TFRCNT 0xffc03830 /* ATAPI DMA mode transfer count */
138 #define ATAPI_UMAIN_TFRCNT 0xffc03834 /* ATAPI UDMAIN transfer count */
139 #define ATAPI_UDMAOUT_TFRCNT 0xffc03838 /* ATAPI UDMAOUT transfer count */
371 #define USB_DMA0COUNTLOW 0xffc04010 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
372 #define USB_DMA0COUNTHIGH 0xffc04014 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
379 #define USB_DMA1COUNTLOW 0xffc04030 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
380 #define USB_DMA1COUNTHIGH 0xffc04034 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
387 #define USB_DMA2COUNTLOW 0xffc04050 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
388 #define USB_DMA2COUNTHIGH 0xffc04054 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
395 #define USB_DMA3COUNTLOW 0xffc04070 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
396 #define USB_DMA3COUNTHIGH 0xffc04074 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
403 #define USB_DMA4COUNTLOW 0xffc04090 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
404 #define USB_DMA4COUNTHIGH 0xffc04094 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
411 #define USB_DMA5COUNTLOW 0xffc040b0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
412 #define USB_DMA5COUNTHIGH 0xffc040b4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
419 #define USB_DMA6COUNTLOW 0xffc040d0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
420 #define USB_DMA6COUNTHIGH 0xffc040d4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
427 #define USB_DMA7COUNTLOW 0xffc040f0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
428 #define USB_DMA7COUNTHIGH 0xffc040f4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
629 #define PIO_XFER_ON 0x1 /* PIO transfer in progress */
630 #define MULTI_XFER_ON 0x2 /* Multi-word DMA transfer in progress */
631 #define ULTRA_XFER_ON 0x4 /* Ultra DMA transfer in progress */
641 #define PIO_DONE_MASK 0x2 /* PIO transfer done interrupt mask */
642 #define MULTI_DONE_MASK 0x4 /* Multi-DMA transfer done interrupt mask */
643 #define UDMAIN_DONE_MASK 0x8 /* Ultra-DMA in transfer done interrupt mask */
644 #define UDMAOUT_DONE_MASK 0x10 /* Ultra-DMA out transfer done interrupt mask */
645 #define HOST_TERM_XFER_MASK 0x20 /* Host terminate current transfer interrupt mask */
646 #define MULTI_TERM_MASK 0x40 /* Device terminate Multi-DMA transfer interrupt mask */
647 #define UDMAIN_TERM_MASK 0x80 /* Device terminate Ultra-DMA-in transfer interrupt mask */
648 #define UDMAOUT_TERM_MASK 0x100 /* Device terminate Ultra-DMA-out transfer interrupt mask */
653 #define PIO_DONE_INT 0x2 /* PIO transfer done interrupt status */
654 #define MULTI_DONE_INT 0x4 /* Multi-DMA transfer done interrupt status */
655 #define UDMAIN_DONE_INT 0x8 /* Ultra-DMA in transfer done interrupt status */
656 #define UDMAOUT_DONE_INT 0x10 /* Ultra-DMA out transfer done interrupt status */
657 #define HOST_TERM_XFER_INT 0x20 /* Host terminate current transfer interrupt status */
658 #define MULTI_TERM_INT 0x40 /* Device terminate Multi-DMA transfer interrupt status */
659 #define UDMAIN_TERM_INT 0x80 /* Device terminate Ultra-DMA-in transfer interrupt status */
660 #define UDMAOUT_TERM_INT 0x100 /* Device terminate Ultra-DMA-out transfer interrupt status */
983 #define PROTOCOL_T 0xc /* transfer type */
992 #define PROTOCOL_R 0xc /* transfer type */
1012 #define DIRECTION 0x2 /* direction of DMA transfer */
1028 #define DMA_COUNT_HIGH 0xffff /* Upper 16-bits of byte count of DMA transfer for DMA master channel */
1032 #define DMA_COUNT_LOW 0xffff /* Lower 16-bits of byte count of DMA transfer for DMA master channel */
/linux-4.1.27/drivers/dma/sh/
H A Drcar-dmac.c30 * struct rcar_dmac_xfer_chunk - Descriptor for a hardware transfer
34 * @size: transfer size in bytes
45 * struct rcar_dmac_hw_desc - Hardware descriptor for a transfer chunk
48 * @tcr: value of the TCR register (transfer count)
60 * @direction: direction of the DMA transfer
61 * @xfer_shift: log2 of the transfer size
62 * @chcr: value of the channel configuration register for this transfer
64 * @chunks: list of transfer chunks for this transfer
65 * @running: the transfer chunk being currently processed
66 * @nchunks: number of transfer chunks for this transfer
67 * @hwdescs.use: whether the transfer descriptor uses hardware descriptors
68 * @hwdescs.mem: hardware descriptors memory for the transfer
71 * @size: transfer size in bytes
72 * @cyclic: when set indicates that the DMA transfer is cyclic
102 * @chunks: array of transfer chunk descriptors
137 * @desc.chunks_free: list of free transfer chunk descriptors
267 /* Hardcode the MEMCPY transfer size to 4 bytes. */
348 * first descriptor at beginning of transfer by the DMAC like it rcar_dmac_chan_start_xfer()
368 * and the transfer completion interrupt. rcar_dmac_chan_start_xfer()
494 * rcar_dmac_desc_put - Release a DMA transfer descriptor
498 * Put the descriptor and its transfer chunk descriptors back in the channel's
548 * rcar_dmac_desc_get - Allocate a descriptor for a DMA transfer
589 * rcar_dmac_xfer_chunk_alloc - Allocate a page worth of transfer chunks
618 * rcar_dmac_xfer_chunk_get - Allocate a transfer chunk for a DMA transfer
623 * Return: A pointer to the allocated transfer chunk descriptor or NULL if no
813 * rcar_dmac_chan_prep_sg - prepare transfer descriptors from an SG list
852 * Allocate and fill the transfer chunk descriptors. We own the only rcar_dmac_chan_prep_sg()
922 * The highmem check currently covers the whole transfer. As an
1148 * If the cookie doesn't correspond to the currently running transfer rcar_dmac_chan_get_residue()
1219 * If no transfer is running pick the first descriptor from the active rcar_dmac_issue_pending()
1220 * list and start the transfer. rcar_dmac_issue_pending()
1270 * descriptor when a transfer end interrupt is triggered. Warn rcar_dmac_isr_transfer_end()
1277 * The transfer end interrupt isn't generated for each chunk when using rcar_dmac_isr_transfer_end()
1283 * If we haven't completed the last transfer chunk simply move rcar_dmac_isr_transfer_end()
1284 * to the next one. Only wake the IRQ thread if the transfer is rcar_dmac_isr_transfer_end()
1295 * We've completed the last transfer chunk. If the transfer is rcar_dmac_isr_transfer_end()
1478 * TODO: Wait for the current transfer to complete and stop the device. rcar_dmac_sleep_suspend()
1694 * Default transfer size of 32 bytes requires 32-byte alignment. rcar_dmac_probe()
H A Dshdma.h51 u32 tcr; /* TCR / transfer count */
H A Dusb-dmac.c33 * struct usb_dmac_sg - Descriptor for a hardware transfer
35 * @size: transfer size in bytes
45 * @direction: direction of the DMA transfer
49 * @residue: residue after the DMAC completed a transfer
51 * @done_cookie: cookie after the DMAC completed a transfer
52 * @sg: information for the transfer
77 * @desc_freed: freed descriptors after the DMAC completed a transfer
237 * will get the previous value from vchan_next_desc() after a transfer usb_dmac_chan_start_desc()
594 /* Restart the next transfer if this driver has a next desc */ usb_dmac_isr_transfer_end()
831 * Default transfer size of 32 bytes requires 32-byte alignment. usb_dmac_probe()
/linux-4.1.27/drivers/media/usb/au0828/
H A Dau0828.h58 /* Defination for AU0828 USB transfer */
142 /* transfer buffers for isoc transfer */
263 /* usb transfer */
269 char *transfer_buffer[AU0828_MAX_ISO_BUFS];/* transfer buffers for isoc
270 transfer */
276 /* Preallocated transfer digital transfer buffers */
/linux-4.1.27/drivers/media/usb/tm6000/
H A Dtm6000-usb-isoc.h34 /* transfer buffers for isoc transfer */
/linux-4.1.27/drivers/scsi/arm/
H A Darxescsi.c62 * min_type - minimum DMA support that we must have for this transfer
63 * Returns : 0 if we should not set CMD_WITHDMA for transfer info command
104 * Function: int arxescsi_dma_pseudo(host, SCpnt, direction, transfer)
109 * transfer - minimum number of bytes we expect to transfer
113 fasdmadir_t direction, int transfer) arxescsi_dma_pseudo()
156 if (transfer && (transfer & 255)) { arxescsi_dma_pseudo()
112 arxescsi_dma_pseudo(struct Scsi_Host *host, struct scsi_pointer *SCp, fasdmadir_t direction, int transfer) arxescsi_dma_pseudo() argument
H A Dacornscsi.h223 * Synchronous transfer state
225 typedef enum { /* Synchronous transfer state */
324 unsigned char sync_xfer; /* synchronous transfer (SBIC value) */
333 unsigned int start_addr; /* start address of current transfer */
336 unsigned int xfer_start; /* scheduled DMA transfer start */
337 unsigned int xfer_length; /* scheduled DMA transfer length */
339 unsigned char xfer_required:1; /* set if we need to transfer something */
H A Dfas216.h22 /* transfer count low */
26 /* transfer count medium */
162 /* High transfer count (read/write) */
248 unsigned int async_stp; /* Async transfer STP value */
275 unsigned char wide_max_size; /* Maximum wide transfer size */
277 unsigned int asyncperiod; /* Async transfer period (ns) */
294 unsigned char stp; /* synchronous transfer period */
296 unsigned char wide_xfer; /* currently negociated wide transfer */
297 neg_t sync_state; /* synchronous transfer mode */
298 neg_t wide_state; /* wide transfer mode */
304 fasdmatype_t transfer_type; /* current type of DMA transfer */
306 void (*pseudo)(struct Scsi_Host *host, struct scsi_pointer *SCp, fasdmadir_t direction, int transfer);
H A Dcumana_2.c16 * 18-08-1998 RMK 0.0.3 Fixed synchronous transfer depth.
153 * min_type - minimum DMA support that we must have for this transfer
154 * Returns : type of transfer to be performed
201 * Prototype: void cumanascsi_2_dma_pseudo(host, SCpnt, direction, transfer)
206 * transfer - minimum number of bytes we expect to transfer
210 fasdmadir_t direction, int transfer) cumanascsi_2_dma_pseudo()
240 if (transfer && (transfer & 255)) { cumanascsi_2_dma_pseudo()
209 cumanascsi_2_dma_pseudo(struct Scsi_Host *host, struct scsi_pointer *SCp, fasdmadir_t direction, int transfer) cumanascsi_2_dma_pseudo() argument
H A Dfas216.c73 * > transfer mode is asynchronous data transfer mode. The default data transfer
460 * fas216_set_sync - setup FAS216 chip for specified transfer period.
464 * Correctly setup FAS216 chip for specified transfer period.
466 * a transfer period >= 200ns - otherwise the chip will violate
483 /* Synchronous transfer support
501 * We will always initiate a synchronous transfer negotiation request on
503 * at some point performed a synchronous transfer negotiation request, or
508 * fas216_handlesync - Handle a synchronous transfer message
512 * Handle a synchronous transfer message from the target
522 /* Synchronous transfer request failed. fas216_handlesync()
540 /* We don't accept synchronous transfer requests. fas216_handlesync()
542 * synchronous transfer agreement from being reached. fas216_handlesync()
548 /* We were not negotiating a synchronous transfer, fas216_handlesync()
574 /* We initiated the synchronous transfer negotiation, fas216_handlesync()
576 * target. The synchronous transfer agreement has been fas216_handlesync()
621 * fas216_updateptrs - update data pointers after transfer suspended/paused
625 * Update data pointers after transfer suspended/paused
660 * fas216_pio - transfer data off of/on to card using programmed IO
661 * @info: interface to transfer data to/from
662 * @direction: direction to transfer data (DMA_OUT/DMA_IN)
697 * fas216_cleanuptransfer - clean up after a transfer has completed.
726 "transfer: length 0x%06x, residual 0x%x, fifo %d", fas216_cleanuptransfer()
730 * If we were performing Data-Out, the transfer counter fas216_cleanuptransfer()
733 * bytes left in the FIFO from the transfer counter. fas216_cleanuptransfer()
742 * fas216_transfer - Perform a DMA/PIO transfer off of/on to card
745 * Start a DMA/PIO transfer off of/on to card
766 * If we have a synchronous transfer agreement in effect, we must fas216_transfer()
792 fas216_log(info, LOG_BUFFER, "PIO transfer"); fas216_transfer()
800 fas216_log(info, LOG_BUFFER, "pseudo transfer"); fas216_transfer()
807 fas216_log(info, LOG_BUFFER, "block dma transfer"); fas216_transfer()
812 fas216_log(info, LOG_BUFFER, "total dma transfer"); fas216_transfer()
824 * fas216_stoptransfer - Stop a DMA transfer onto / off of the card
1127 case EXTENDED_SDTR: /* Sync transfer negotiation request/reply */ fas216_parse_message()
1742 * information transfer phase (message out) for test purposes.
2068 * we do not have any buffers left to transfer. The world fas216_std_done()
2082 "incomplete data transfer detected: res=%08X ptr=%p len=%X\n", fas216_std_done()
2155 * to transfer, we should not have a valid pointer. fas216_done()
2159 "zero bytes left to transfer, but buffer pointer still valid: ptr=%p len=%08x\n", fas216_done()
/linux-4.1.27/drivers/s390/char/
H A Dhmcdrv_ftp.h45 * @buf: kernel-space transfer data buffer, 4k aligned
46 * @len: (max) number of bytes to transfer from/to @buf
H A Dhmcdrv_ftp.c28 * @cmd: FTP transfer function
33 ssize_t (*transfer)(const struct hmcdrv_ftp_cmdspec *ftp, member in struct:hmcdrv_ftp_ops
167 pr_debug("starting transfer, cmd %d for '%s' at %lld with %zd bytes\n", hmcdrv_ftp_do()
169 len = hmcdrv_cache_cmd(ftp, hmcdrv_ftp_funcs->transfer); hmcdrv_ftp_do()
296 .transfer = diag_ftp_cmd hmcdrv_ftp_startup()
302 .transfer = sclp_ftp_cmd hmcdrv_ftp_startup()
H A Dhmcdrv_cache.c107 * hmcdrv_cache_do() - do a HMC drive CD/DVD transfer with cache update
109 * @func: FTP transfer function to be used
167 * hmcdrv_cache_cmd() - perform a cached HMC drive CD/DVD transfer
169 * @func: FTP transfer function to be used
/linux-4.1.27/arch/mips/loongson/common/cs5536/
H A Dcs5536_pci.c57 * write to PCI config space and transfer it to MSR write.
71 * read PCI config space and transfer it to MSR access.
/linux-4.1.27/drivers/net/wan/
H A Dcosa.h40 #define SR_UP_REQUEST 0x02 /* request from SRP to transfer data
42 #define SR_DOWN_REQUEST 0x01 /* SRP is able to transfer data down
45 transfer (up or down) */
55 #define SR_PKT_UP 0x01 /* transfer of packet up in progress */
56 #define SR_PKT_DOWN 0x02 /* transfer of packet down in progress */
/linux-4.1.27/drivers/gpu/drm/via/
H A Dvia_dmablit.h123 #define VIA_DMA_DPR_DT (1<<3) /* direction of transfer (RO) */
127 #define VIA_DMA_MR_TDIE (1<<1) /* transfer done interrupt enable */
132 #define VIA_DMA_CSR_TS (1<<1) /* transfer start */
133 #define VIA_DMA_CSR_TA (1<<2) /* transfer abort */
134 #define VIA_DMA_CSR_TD (1<<3) /* transfer done */
/linux-4.1.27/arch/x86/include/asm/
H A Ddma.h28 * - ALL registers are 8 bits only, regardless of transfer size
33 * - transfer count loaded to registers is 1 less than actual count
60 * Again, channels 5-7 transfer _physical_ words (16 bits), so addresses
79 /* The maximum address that we can perform a DMA transfer to on this platform */
206 /* Set only the page register bits of the transfer address.
239 /* Set transfer address & page bits for specific DMA channel.
255 /* Set transfer size (max 64k for DMA0..3, 128k for DMA5..7) for
279 /* Get DMA residue count. After a DMA transfer, this
280 * should return zero. Reading this while a DMA transfer is
283 * Otherwise, it returns the number of _bytes_ left to transfer.
/linux-4.1.27/arch/mips/include/asm/
H A Ddma.h34 * - ALL registers are 8 bits only, regardless of transfer size
39 * - transfer count loaded to registers is 1 less than actual count
66 * Again, channels 5-7 transfer _physical_ words (16 bits), so addresses
81 * The maximum address in KSEG0 that we can perform a DMA transfer to on this
212 /* Set only the page register bits of the transfer address.
245 /* Set transfer address & page bits for specific DMA channel.
261 /* Set transfer size (max 64k for DMA0..3, 128k for DMA5..7) for
282 /* Get DMA residue count. After a DMA transfer, this
283 * should return zero. Reading this while a DMA transfer is
286 * Otherwise, it returns the number of _bytes_ left to transfer.
/linux-4.1.27/arch/powerpc/platforms/52xx/
H A Dmpc52xx_lpbfifo.c81 /* While the FIFO can be setup for transfer sizes as large as mpc52xx_lpbfifo_kick()
83 * not generate interrupts for FIFO full events (only transfer mpc52xx_lpbfifo_kick()
88 * This driver restricts the size of the transfer mpc52xx_lpbfifo_kick()
162 /* Set transfer size, width, chip select and READ mode */ mpc52xx_lpbfifo_kick()
275 /* Update transfer position and count */ mpc52xx_lpbfifo_irq()
296 * (status & 0x10) {transfer aborted}: This case needs more mpc52xx_lpbfifo_irq()
303 /* When the do_callback flag is set; it means the transfer is finished mpc52xx_lpbfifo_irq()
350 pr_err("transfer stalled\n"); mpc52xx_lpbfifo_bcom_irq()
394 * mpc52xx_lpbfifo_submit - Submit an LPB FIFO transfer request.
406 /* If the req pointer is already set, then a transfer is in progress */ mpc52xx_lpbfifo_submit()
412 /* Setup the transfer */ mpc52xx_lpbfifo_submit()
435 * If the req pointer is already set and a transfer was mpc52xx_lpbfifo_start_xfer()
436 * started on submit, then this transfer is in progress mpc52xx_lpbfifo_start_xfer()
/linux-4.1.27/drivers/usb/host/
H A Dmax3421-hcd.c97 PKT_STATE_TERMINATE /* waiting to terminate control transfer */
246 MAX3421_HI_HXFRDN_BIT, /* host transfer done */
353 struct spi_transfer transfer; spi_rd8() local
356 memset(&transfer, 0, sizeof(transfer)); spi_rd8()
364 transfer.tx_buf = max3421_hcd->tx->data; spi_rd8()
365 transfer.rx_buf = max3421_hcd->rx->data; spi_rd8()
366 transfer.len = 2; spi_rd8()
368 spi_message_add_tail(&transfer, &msg); spi_rd8()
379 struct spi_transfer transfer; spi_wr8() local
382 memset(&transfer, 0, sizeof(transfer)); spi_wr8()
391 transfer.tx_buf = max3421_hcd->tx->data; spi_wr8()
392 transfer.len = 2; spi_wr8()
394 spi_message_add_tail(&transfer, &msg); spi_wr8()
403 struct spi_transfer transfer[2]; spi_rd_buf() local
406 memset(transfer, 0, sizeof(transfer)); spi_rd_buf()
413 transfer[0].tx_buf = max3421_hcd->tx->data; spi_rd_buf()
414 transfer[0].len = 1; spi_rd_buf()
416 transfer[1].rx_buf = buf; spi_rd_buf()
417 transfer[1].len = len; spi_rd_buf()
419 spi_message_add_tail(&transfer[0], &msg); spi_rd_buf()
420 spi_message_add_tail(&transfer[1], &msg); spi_rd_buf()
429 struct spi_transfer transfer[2]; spi_wr_buf() local
432 memset(transfer, 0, sizeof(transfer)); spi_wr_buf()
440 transfer[0].tx_buf = max3421_hcd->tx->data; spi_wr_buf()
441 transfer[0].len = 1; spi_wr_buf()
443 transfer[1].tx_buf = buf; spi_wr_buf()
444 transfer[1].len = len; spi_wr_buf()
446 spi_message_add_tail(&transfer[0], &msg); spi_wr_buf()
447 spi_message_add_tail(&transfer[1], &msg); spi_wr_buf()
596 * Issue the next host-transfer command.
1025 * of a bulk-out transfer if the last transfer was a max3421_transfer_out_done()
1086 * terminate the control transfer: max3421_host_transfer_done()
H A Dfhci-sched.c375 * schedule the next available ISO transfer fhci_schedule_transactions()
376 *or next stage of the ISO transfer fhci_schedule_transactions()
381 * schedule the next available interrupt transfer or fhci_schedule_transactions()
382 * the next stage of the interrupt transfer fhci_schedule_transactions()
387 * schedule the next available control transfer fhci_schedule_transactions()
388 * or the next stage of the control transfer fhci_schedule_transactions()
395 * schedule the next available bulk transfer or the next stage of the fhci_schedule_transactions()
396 * bulk transfer fhci_schedule_transactions()
686 /* transfer complted callback */ fhci_transfer_confirm_callback()
741 /* for ISO transfer calculate start frame index */ fhci_queue_urb()
/linux-4.1.27/drivers/iio/adc/
H A Dmcp320x.c61 struct spi_transfer transfer[2]; member in struct:mcp320x
302 adc->transfer[0].tx_buf = &adc->tx_buf; mcp320x_probe()
303 adc->transfer[0].len = sizeof(adc->tx_buf); mcp320x_probe()
304 adc->transfer[1].rx_buf = adc->rx_buf; mcp320x_probe()
305 adc->transfer[1].len = sizeof(adc->rx_buf); mcp320x_probe()
307 spi_message_init_with_transfers(&adc->msg, adc->transfer, mcp320x_probe()
308 ARRAY_SIZE(adc->transfer)); mcp320x_probe()
/linux-4.1.27/drivers/mmc/host/
H A Datmel-mci-regs.h59 # define ATMCI_CMDR_START_XFER ( 1 << 16) /* Start data transfer */
60 # define ATMCI_CMDR_STOP_XFER ( 2 << 16) /* Stop data transfer */
63 # define ATMCI_CMDR_BLOCK ( 0 << 19) /* Single-block transfer */
64 # define ATMCI_CMDR_MULTI_BLOCK ( 1 << 19) /* Multi-block transfer */
65 # define ATMCI_CMDR_STREAM ( 2 << 19) /* MMC Stream transfer */
66 # define ATMCI_CMDR_SDIO_BYTE ( 4 << 19) /* SDIO Byte transfer */
67 # define ATMCI_CMDR_SDIO_BLOCK ( 5 << 19) /* SDIO Block transfer */
H A Dmmci_qcom_dml.c143 * if data transfer is to happen in PIO mode and don't dml_hw_init()
153 * Disable infinite mode transfer as we won't be doing any dml_hw_init()
154 * infinite size data transfers. All data transfer will be dml_hw_init()
/linux-4.1.27/arch/parisc/include/asm/
H A Ddma.h25 /* The maximum address that we can perform a DMA transfer to on this platform
83 /* Get DMA residue count. After a DMA transfer, this
84 * should return zero. Reading this while a DMA transfer is
87 * Otherwise, it returns the number of _bytes_ left to transfer.
145 /* Set only the page register bits of the transfer address.
155 /* Set transfer address & page bits for specific DMA channel.
163 /* Set transfer size (max 64k for DMA1..3, 128k for DMA5..7) for
/linux-4.1.27/arch/m68k/include/asm/
H A Ddvma.h90 __volatile__ unsigned long st_addr; /* Start address of this transfer */
91 __volatile__ unsigned long cnt; /* How many bytes to transfer */
120 unsigned long addr; /* Start address of current transfer */
121 int nbytes; /* Size of current transfer */
172 #define DMA_2CLKS 0x00200000 /* Each transfer = 2 clock ticks */
173 #define DMA_3CLKS 0x00400000 /* Each transfer = 3 clock ticks */
192 /* Determine highest possible final transfer address given a base */
H A Dtraps.h157 /* bus access transfer type codes */
172 #define MMU060_LK (0x02000000) /* locked transfer */
178 #define MMU060_SIZ (0x00600000) /* transfer size */
179 #define MMU060_TT (0x00180000) /* transfer type (TT) bits */
180 #define MMU060_TM (0x00070000) /* transfer modifier (TM) bits */
H A Dmcfdma.h58 #define MCFDMA_DCR_START 0x0001 /* Start transfer */
68 #define MCFDMA_DSR_DONE 0x01 /* DMA transfer complete */
112 #define MCFDMA_DIR_TCEN 0x0100 /* Transfer Complete (a bus transfer, that is) interrupt enable */
H A Ddma.h211 /* Set transfer address for specific DMA channel */ set_dma_addr()
274 * Get DMA residue count. After a DMA transfer, this
275 * should return zero. Reading this while a DMA transfer is
277 * Otherwise, it returns the number of _bytes_ left to transfer.
300 * are dual address transfer, and there is no 'device' setup or direction bit.
314 * for you, but don't mix them in the same transfer setup.
397 /* Set transfer address for specific DMA channel */ set_dma_addr()
460 * Get DMA residue count. After a DMA transfer, this
461 * should return zero. Reading this while a DMA transfer is
463 * Otherwise, it returns the number of _bytes_ left to transfer.
/linux-4.1.27/arch/alpha/include/asm/
H A Ddma.h33 * - ALL registers are 8 bits only, regardless of transfer size
38 * - transfer count loaded to registers is 1 less than actual count
65 * Again, channels 5-7 transfer _physical_ words (16 bits), so addresses
84 /* The maximum address for ISA DMA transfer on Alpha XL, due to an
89 /* The maximum address for ISA DMA transfer on RUFFIAN,
94 /* The maximum address for ISA DMA transfer on SABLE, and some ALCORs,
262 /* Set only the page register bits of the transfer address.
301 /* Set transfer address & page bits for specific DMA channel.
317 /* Set transfer size (max 64k for DMA1..3, 128k for DMA5..7) for
338 /* Get DMA residue count. After a DMA transfer, this
339 * should return zero. Reading this while a DMA transfer is
342 * Otherwise, it returns the number of _bytes_ left to transfer.
/linux-4.1.27/drivers/media/dvb-frontends/
H A Dmb86a16.c144 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); CNTM_set()
171 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); smrt_set()
182 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); srst()
198 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); afcex_data_set()
214 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); afcofs_data_set()
227 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); stlp_set()
240 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); Vi_set()
282 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); initial_set()
295 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); S01T_set()
312 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); EN_set()
337 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); AFCEXEN_set()
351 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); DAGC_data_set()
455 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); signal_det()
544 dprintk(verbose, MB86A16_ERROR, 1, "RF Setup - I2C transfer error"); rf_val_set()
573 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); afcerr_chk()
592 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); dagcm_val_get()
629 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); mb86a16_read_status()
648 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); sync_chk()
735 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); freqerr_chk()
972 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); SEQ_set()
983 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); iq_vt_set()
993 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); FEC_srst()
1003 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); S2T_set()
1013 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); S45T_set()
1205 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); mb86a16_set_fe()
1444 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); mb86a16_set_fe()
1561 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); mb86a16_send_diseqc_msg()
1589 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); mb86a16_send_diseqc_burst()
1622 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); mb86a16_set_tone()
1722 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); mb86a16_read_ber()
1733 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); mb86a16_read_signal_strength()
1782 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); mb86a16_read_snr()
1805 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); mb86a16_read_ucblocks()
H A Ddib3000.h37 /* pid and transfer handling is done in the demodulator */
H A Dlgdt330x.h50 /* Flip the polarity of the mpeg data transfer clock using alternate init data
/linux-4.1.27/drivers/media/usb/dvb-usb/
H A Ddigitv.h15 * First byte describes the command. Reads are 2 consecutive transfer (as always).
H A Ddw2102.c38 /* Max transfer size done by I2C transfer functions */
724 err("i2c transfer failed."); su3000_i2c_transfer()
729 err("i2c transfer failed."); su3000_i2c_transfer()
743 err("i2c transfer failed."); su3000_i2c_transfer()
757 err("i2c transfer failed."); su3000_i2c_transfer()
1361 err("command 0x0e transfer failed."); su3000_frontend_attach()
1368 err("command 0x0e transfer failed."); su3000_frontend_attach()
1376 err("command 0x0e transfer failed."); su3000_frontend_attach()
1383 err("command 0x0e transfer failed."); su3000_frontend_attach()
1388 err("command 0x51 transfer failed."); su3000_frontend_attach()
1412 err("command 0x0e transfer failed."); t220_frontend_attach()
1419 err("command 0x0e transfer failed."); t220_frontend_attach()
1426 err("command 0x0e transfer failed."); t220_frontend_attach()
1435 err("command 0x0e transfer failed."); t220_frontend_attach()
1440 err("command 0x51 transfer failed."); t220_frontend_attach()
1462 err("command 0x51 transfer failed."); m88rs2000_frontend_attach()
1493 err("command 0x0e transfer failed."); tt_s2_4600_frontend_attach()
1500 err("command 0x0e transfer failed."); tt_s2_4600_frontend_attach()
1508 err("command 0x0e transfer failed."); tt_s2_4600_frontend_attach()
1515 err("command 0x0e transfer failed."); tt_s2_4600_frontend_attach()
1520 err("command 0x51 transfer failed."); tt_s2_4600_frontend_attach()
1817 /* parameter for the MPEG2-data transfer */
1872 /* parameter for the MPEG2-data transfer */
1923 /* parameter for the MPEG2-data transfer */
H A Dcxusb.c48 /* Max transfer size done by I2C transfer functions */
1627 /* parameter for the MPEG2-data transfer */
1662 /* use usb alt setting 0 for EP4 transfer (dvb-t),
1663 use usb alt setting 7 for EP2 transfer (atsc) */
1676 /* parameter for the MPEG2-data transfer */
1719 /* use usb alt setting 0 for EP4 transfer (dvb-t),
1720 use usb alt setting 7 for EP2 transfer (atsc) */
1732 /* parameter for the MPEG2-data transfer */
1783 /* use usb alt setting 0 for EP4 transfer (dvb-t),
1784 use usb alt setting 7 for EP2 transfer (atsc) */
1797 /* parameter for the MPEG2-data transfer */
1838 /* use usb alt setting 0 for EP4 transfer (dvb-t),
1839 use usb alt setting 7 for EP2 transfer (atsc) */
1852 /* parameter for the MPEG2-data transfer */
1903 /* parameter for the MPEG2-data transfer */
1956 /* parameter for the MPEG2-data transfer */
2011 /* parameter for the MPEG2-data transfer */
2063 /* parameter for the MPEG2-data transfer */
2109 /* parameter for the MPEG2-data transfer */
2162 /* parameter for the MPEG2-data transfer */
2216 /* parameter for the MPEG2-data transfer */
2269 /* parameter for the MPEG2-data transfer */
H A Ddtt200u.c151 /* parameter for the MPEG2-data transfer */
201 /* parameter for the MPEG2-data transfer */
251 /* parameter for the MPEG2-data transfer */
301 /* parameter for the MPEG2-data transfer */
H A Ddtt200u.h45 * 08 - transfer switch
/linux-4.1.27/drivers/staging/comedi/drivers/
H A Dni_labpc_isadma.c33 /* utility function that suggests a dma transfer size in bytes */ labpc_suggest_transfer_size()
68 /* set appropriate size of transfer */ labpc_setup_dma()
95 * transfer. It should always be zero at this point unless labpc_drain_dma()
101 * Figure out how many samples to read for this transfer and labpc_drain_dma()
H A Dcomedi_isadma.c27 * comedi_isadma_program - program and enable an ISA DMA transfer
48 * Returns the residue (remaining bytes) left in the DMA transfer.
69 * Returns the residue (remaining bytes) left in the DMA transfer.
104 * comedi_isadma_poll - poll the current DMA transfer
107 * Returns the position (in bytes) of the current DMA transfer.
141 * comedi_isadma_set_mode - set the ISA DMA transfer direction
/linux-4.1.27/drivers/usb/dwc2/
H A Dhcd.h76 * @xfer_buf: Pointer to current transfer buffer position
80 * @xfer_len: Total number of bytes to transfer
82 * @start_pkt_count: Packet count at start of transfer
83 * @xfer_started: True if the transfer has been started
102 * assigned to the current transfer (not counting PINGs)
104 * @ntd: Number of transfer descriptors for the transfer
107 * @qh: QH for the transfer being processed by this channel
112 * host mode. It contains the data items needed to transfer packets to an
235 * @td_first: Index of first activated isochronous transfer descriptor
236 * @td_last: Index of last activated isochronous transfer descriptor
239 * @sched_frame: (Micro)frame to initialize a periodic transfer.
240 * The transfer executes in the following (micro)frame.
243 * @ntd: Actual number of transfer descriptors in a list
252 * @desc_list: List of transfer descriptors
254 * @n_bytes: Xfer Bytes array. Each element corresponds to a transfer
292 * struct dwc2_qtd - Software queue transfer descriptor (QTD)
299 * transfer types. One of the following values:
306 * transfer. A frame descriptor describes the buffer
308 * next scheduled (micro)frame of an isochronous transfer.
315 * a transaction within this transfer
319 * @urb: URB for this transfer
324 * interrupt, or isochronous transfer. A single QTD is created for each URB
325 * (of one of these types) submitted to the HCD. The transfer associated with
695 * also shown for start transfer and two additional sample points.
H A Dhcd_intr.c392 * Gets the actual length of a transfer after the transfer halts. halt_status
427 * always an integral number of packets if the transfer was dwc2_get_actual_xfer_length()
443 * Sets the URB status if the data transfer is finished.
445 * Return: 1 if the data transfer specified by the URB is completely finished,
501 * Save the starting data toggle for the next transfer. The data toggle is
527 * the transfer is stopped for any reason. The fields of the current entry in
528 * the frame descriptor array are set based on the transfer state and the input
670 * freed if the transfer is complete or an error has occurred.
748 * here. That's done when a periodic transfer is dwc2_release_channel()
847 * Got a NYET on the last transaction of the transfer. This dwc2_complete_non_periodic_xfer()
849 * beginning of the next transfer. dwc2_complete_non_periodic_xfer()
858 * transfer or more data packets for a bulk transfer at this point, dwc2_complete_non_periodic_xfer()
860 * to the transfer when the non-periodic schedule is processed after dwc2_complete_non_periodic_xfer()
1014 " Control data transfer done\n"); dwc2_hc_xfercomp_intr()
1022 dev_vdbg(hsotg->dev, " Control transfer complete\n"); dwc2_hc_xfercomp_intr()
1034 dev_vdbg(hsotg->dev, " Bulk transfer complete\n"); dwc2_hc_xfercomp_intr()
1049 dev_vdbg(hsotg->dev, " Interrupt transfer complete\n"); dwc2_hc_xfercomp_intr()
1054 * Interrupt URB is done on the first transfer complete dwc2_hc_xfercomp_intr()
1070 dev_vdbg(hsotg->dev, " Isochronous transfer complete\n"); dwc2_hc_xfercomp_intr()
1132 * Updates the state of the URB when a transfer has been stopped due to an
1133 * abnormal condition before the transfer completes. Modifies the
1191 * interrupt. Re-start the SSPLIT transfer. dwc2_hc_nak_intr()
1232 * Halt the channel so the transfer can be re-started from dwc2_hc_nak_intr()
1244 dev_err(hsotg->dev, "NACK interrupt for ISOC transfer\n"); dwc2_hc_nak_intr()
1312 * Halt the channel so the transfer can be re-started dwc2_hc_ack_intr()
1315 * when the transfer is started because the core dwc2_hc_ack_intr()
1316 * automatically executes the PING, then the transfer. dwc2_hc_ack_intr()
1406 * Halt the channel and re-start the transfer so the PING protocol dwc2_hc_nyet_intr()
1585 * Halt the channel so the transfer can be re-started from dwc2_hc_xacterr_intr()
1659 "Data Toggle Error on OUT transfer, channel %d\n", dwc2_hc_datatglerr_intr()
1766 * transfer timeout. In the case of an AHB Error, the dwc2_hc_chhltd_intr_dma()
1833 * transfer is in an error state. In that case, the nak dwc2_hc_chhltd_intr_dma()
1843 * transfer is in an error state. In that case, the ack dwc2_hc_chhltd_intr_dma()
1853 * A periodic transfer halted with no other dwc2_hc_chhltd_intr_dma()
1859 "%s: Halt channel %d (assume incomplete periodic transfer)\n", dwc2_hc_chhltd_intr_dma()
1896 * processing a transfer on a channel. Other host channel interrupts (except
H A Dhcd_queue.c242 * periodic transfer
429 * dwc2_check_max_xfer_size() - Checks that the max transfer size allowed in a
430 * host channel is large enough to handle the maximum data transfer in a single
431 * (micro)frame for a periodic transfer
459 * dwc2_schedule_periodic() - Schedules an interrupt or isochronous transfer in
463 * @qh: QH for the periodic transfer. The QH should already contain the
493 "%s: No host channel available for periodic transfer\n", dwc2_schedule_periodic()
503 "%s: Insufficient periodic bandwidth for periodic transfer\n", dwc2_schedule_periodic()
511 "%s: Channel max transfer size too small for periodic transfer\n", dwc2_schedule_periodic()
535 * dwc2_deschedule_periodic() - Removes an interrupt or isochronous transfer
539 * @qh: QH for the periodic transfer
640 * Schedule the next continuing periodic split transfer
H A Dhcd_ddma.c394 * Determine starting frame for Isochronous transfer.
453 * Calculate initial descriptor index for isochronous transfer based on
634 /* Need 1 packet for transfer length of 0 */ dwc2_fill_host_dma_desc()
651 * Last (or only) descriptor of IN transfer with actual size less dwc2_fill_host_dma_desc()
674 * if SG transfer consists of multiple URBs, this pointer is re-assigned dwc2_init_non_isoc_dma_desc()
735 * dwc2_hcd_start_xfer_ddma() - Starts a transfer in Descriptor DMA mode
743 * transfer. For Interrupt and Isochronous endpoints, initializes descriptor
747 * on the scheduled frame, but only on the first transfer descriptor within a
748 * session. Then the transfer is started via enabling the channel.
888 * queing transfer requests. dwc2_complete_isoc_xfer_ddma()
1062 " Control data transfer done\n"); dwc2_process_non_isoc_desc()
1128 * Got a NYET on the last transaction of the transfer. dwc2_complete_non_isoc_xfer_ddma()
1130 * state at the beginning of the next transfer. dwc2_complete_non_isoc_xfer_ddma()
1143 * @chan: Host channel the transfer is completed on
1174 /* Keep in assigned schedule to continue transfer */ dwc2_hcd_complete_xfer_ddma()
H A Dcore.c924 * Host channel interrupts that may need to be serviced while this transfer is
942 /* Enable channel interrupts required for this transfer */ dwc2_hc_init()
947 * the current transfer dwc2_hc_init()
1021 * This function should only be called in Slave mode or to abort a transfer in
1023 * controller halts the channel when the transfer is complete or a condition
1056 * and QH state associated with this transfer has been cleared dwc2_hc_halt()
1083 * started yet. In DMA mode, the transfer may halt if dwc2_hc_halt()
1087 * it's possible that the transfer has been assigned dwc2_hc_halt()
1098 * happen when a transfer is aborted by a higher level in dwc2_hc_halt()
1180 * dwc2_hc_cleanup() - Clears the transfer state for a host channel
1185 * This function is normally called after a transfer is done and the host
1206 * which frame a periodic transfer should occur
1227 /* Set up the initial PID for the transfer */ dwc2_set_pid_isoc()
1302 * dwc2_hc_start_transfer() - Does the setup for a data transfer for a host
1303 * channel and starts the transfer
1315 * For an OUT transfer in Slave mode, it loads a data packet into the
1319 * For an IN transfer in Slave mode, a data packet is requested. The data
1323 * For a PING transfer in Slave mode, the Do Ping bit is set in the HCTSIZ
1326 * simply set to 0 since no data transfer occurs in this case.
1328 * For a PING transfer in DMA mode, the HCTSIZ register is initialized with
1329 * all the information required to perform the subsequent data transfer. In
1332 * transfer.
1382 * Ensure that the transfer length and packet count will fit dwc2_hc_start_transfer()
1388 * Make sure the transfer size is no larger than one dwc2_hc_start_transfer()
1390 * when the periodic transfer was accepted to ensure dwc2_hc_start_transfer()
1416 /* Need 1 packet for transfer length of 0 */ dwc2_hc_start_transfer()
1431 * actual transfer length dwc2_hc_start_transfer()
1523 * dwc2_hc_start_transfer_ddma() - Does the setup for a data transfer for a
1524 * host channel and starts the transfer in Descriptor DMA mode
1529 * Initializes HCTSIZ register. For a PING transfer the Do Ping bit is set.
1534 * starts the transfer via enabling the channel.
1607 * dwc2_hc_continue_transfer() - Continues a data transfer that was started by
1618 * For an OUT transfer, a new data packet is loaded into the appropriate FIFO
1619 * if there is any data remaining to be queued. For an IN transfer, another
1620 * data packet is always requested. For the SETUP phase of a control transfer,
1624 * for this transfer
1651 * transfer completes, the extra requests for the channel will dwc2_hc_continue_transfer()
1689 * dwc2_hc_do_ping() - Starts a PING transfer
/linux-4.1.27/include/linux/hsi/
H A Dhsi.h57 HSI_STATUS_COMPLETED, /* Message transfer is completed */
59 HSI_STATUS_PROCEEDING, /* Message transfer is ongoing */
61 HSI_STATUS_ERROR, /* Error when message transfer was ongoing */
189 * @cl: HSI device client that issues the transfer
191 * @context: Client context data associated to the transfer
194 * @status: Status of the transfer when completed
229 * @async: Asynchronous transfer callback
394 * hsi_async_read - Submit a read transfer
396 * @msg: HSI message descriptor of the transfer
407 * hsi_async_write - Submit a write transfer
409 * @msg: HSI message descriptor of the transfer
/linux-4.1.27/drivers/gpio/
H A Dgpio-max7301.c21 /* A write to the MAX7301 means one message with one transfer */ max7301_spi_write()
44 * This relies on the fact, that a transfer with NULL tx_buf shifts out max7301_spi_read()
/linux-4.1.27/drivers/char/xilinx_hwicap/
H A Dbuffer_icap.c47 /* Constants for checking transfer status */
53 /* Size of transfer, read & write */
57 /* Read not Configure, direction of transfer. Write only */
59 /* Indicates transfer complete. Read only */
126 * The size register holds the number of 8 bit bytes to transfer between
140 * The bram offset register holds the starting bram address to transfer
154 * The RNC register determines the direction of the data transfer. It
156 * this register initiates the transfer. A value of 1 initiates a
/linux-4.1.27/include/sound/
H A Dcs8427.h128 #define CS8427_DETC (1<<2) /* D to E C-buffer transfer interrupt */
129 #define CS8427_EFTC (1<<1) /* E to F C-buffer transfer interrupt */
133 #define CS8427_DETU (1<<3) /* D to E U-buffer transfer interrupt */
134 #define CS8427_EFTU (1<<2) /* E to F U-buffer transfer interrupt */
169 #define CS8427_DETCI (1<<3) /* D to E CS data buffer transfer inhibit bit, 0 = allow, 1 = inhibit */
170 #define CS8427_EFTCI (1<<2) /* E to F CS data buffer transfer inhibit bit, 0 = allow, 1 = inhibit */
179 #define CS8427_DETUI (1<<1) /* D to E U-data buffer transfer inhibit bit, 0 = allow, 1 = inhibit */
180 #define CS8427_EFTUI (1<<1) /* E to F U-data buffer transfer inhibit bit, 0 = allow, 1 = inhibit */
H A Di2c.h40 void (*start)(struct snd_i2c_bus *bus); /* transfer start */
41 void (*stop)(struct snd_i2c_bus *bus); /* transfer stop */
/linux-4.1.27/include/linux/mfd/
H A Dviperboard.h72 u16 tf1; /* transfer 1 length */
73 u16 tf2; /* transfer 2 length */
H A Ddln2.h51 * @pdev - the sub-device which is issuing this transfer
70 * @pdev - the sub-device which is issuing this transfer
89 * @pdev - the sub-device which is issuing this transfer
/linux-4.1.27/drivers/mmc/card/
H A Dmmc_test.c67 * @max_tfr: maximum transfer size allowed by driver (in bytes)
88 * struct mmc_test_transfer_result - transfer results for performance tests.
92 * @ts: time values of transfer
93 * @rate: calculated transfer rate
111 * @tr_lst: transfer measurements if any as mmc_test_transfer_result
136 * @scratch: transfer buffer
137 * @buffer: transfer buffer
188 * Fill in the mmc_request structure given a set of transfer parameters.
494 * Calculate transfer rate in bytes per second.
520 * Save transfer results for future usage
545 * Print the transfer rate.
569 * Print the average transfer rate.
673 * Modifies the mmc_request to perform the "short transfer" tests
691 * Checks that a normal transfer didn't have any errors
730 * Checks that a "short transfer" behaved as expected
764 * Tests nonblock transfer with certain parameters
843 * Tests a basic transfer with certain parameters
869 * Tests a transfer where the card will fail completely or partly
898 * Does a complete transfer test where data is also validated
1459 * Map and transfer bytes for multiple transfers.
1472 * In the case of a maximally scattered transfer, the maximum transfer mmc_test_area_io_seq()
1597 * Try to allocate enough memory for a max. sized transfer. Less is OK mmc_test_area_init()
1661 * a single large transfer.
1664 * transfer but with no contiguous pages in the scatter list. This tests
1709 * Single read performance by transfer size.
1730 * Single write performance by transfer size.
1757 * Single trim performance by transfer size.
1814 * Consecutive read performance by transfer size.
1856 * Consecutive write performance by transfer size.
1874 * Consecutive trim performance by transfer size.
1995 * Random read performance by transfer size.
2003 * Random write performance by transfer size.
2021 * In the case of a maximally scattered transfer, the maximum transfer mmc_test_seq_perf()
2554 .name = "Single read performance by transfer size",
2561 .name = "Single write performance by transfer size",
2568 .name = "Single trim performance by transfer size",
2575 .name = "Consecutive read performance by transfer size",
2582 .name = "Consecutive write performance by transfer size",
2589 .name = "Consecutive trim performance by transfer size",
2596 .name = "Random read performance by transfer size",
2603 .name = "Random write performance by transfer size",
/linux-4.1.27/drivers/usb/gadget/udc/
H A Dmv_u3d.h17 /* ep0 transfer state */
152 /* transfer status registers */
156 u32 statuslo; /* transfer status low */
157 u32 statushi; /* transfer status high */
164 u32 endcomplete; /* endpoint transfer complete register */
230 u32 trb_len; /* transfer length */
H A Ds3c-hsudc.c10 * can be configured for Bulk or Interrupt transfer mode.
122 * struct s3c_hsudc_req - Driver encapsulation of USB gadget transfer request.
123 * @req: Reference to USB gadget transfer request.
240 * s3c_hsudc_complete_request - Complete a transfer request.
243 * @status: Transfer completion status for the transfer request.
269 * @status: Transfer completion status for the transfer request.
286 * All the endpoints are stopped and any pending transfer requests if any on
324 * s3c_hsudc_write_fifo - Write next chunk of transfer data to EP fifo.
328 * Write the next chunk of data from a transfer request to the endpoint FIFO.
329 * If the transfer request completes, 1 is returned, otherwise 0 is returned.
374 * transfer request buffer. If the transfer request completes, 1 is returned,
498 * transfer requests, transfers are started.
748 * any is cleared, transfer type is configured and endpoint interrupt is
827 * Allocates a single transfer request structure when called from gadget driver.
847 * Allocates a single transfer request structure when called from gadget driver.
859 * s3c_hsudc_queue - Queue a transfer request for the endpoint.
922 * s3c_hsudc_dequeue - Dequeue a transfer request from an endpoint.
/linux-4.1.27/drivers/mfd/
H A Dcros_ec_spi.c36 * SPI transfer size is 256 bytes, so at 5MHz we need a response
45 * on the other end and need to transfer ~256 bytes, then we need:
78 * @last_transfer_ns: time that we last finished a transfer, or 0 if there
140 dev_err(ec_dev->dev, "spi transfer failed: %d\n", ret); cros_ec_spi_receive_response()
156 * gives us one last shot at getting the transfer and is useful cros_ec_spi_receive_response()
184 * maximum-supported transfer size. cros_ec_spi_receive_response()
202 dev_err(ec_dev->dev, "spi transfer failed: %d\n", ret); cros_ec_spi_receive_response()
220 * @ec_msg: Message to transfer
260 dev_err(ec_dev->dev, "spi transfer failed: %d\n", ret); cros_ec_cmd_xfer_spi()
277 dev_err(ec_dev->dev, "spi transfer failed: %d\n", ret); cros_ec_cmd_xfer_spi()
/linux-4.1.27/arch/mips/include/asm/mach-au1x00/
H A Dau1000_dma.h263 * transfer size, device FIFO width, and coherency settings. set_dma_mode()
339 * Set Buffer 0 transfer address for specific DMA channel.
351 * Set Buffer 1 transfer address for specific DMA channel.
364 * Set Buffer 0 transfer size (max 64k) for a specific DMA channel.
377 * Set Buffer 1 transfer size (max 64k) for a specific DMA channel.
390 * Set both buffer transfer sizes (max 64k) for a specific DMA channel.
430 * Get DMA residue count. Returns the number of _bytes_ left to transfer.
/linux-4.1.27/arch/blackfin/mach-bf527/include/mach/
H A DdefBF525.h194 #define USB_DMA0COUNTLOW 0xffc03c10 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
195 #define USB_DMA0COUNTHIGH 0xffc03c14 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
202 #define USB_DMA1COUNTLOW 0xffc03c30 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
203 #define USB_DMA1COUNTHIGH 0xffc03c34 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
210 #define USB_DMA2COUNTLOW 0xffc03c50 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
211 #define USB_DMA2COUNTHIGH 0xffc03c54 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
218 #define USB_DMA3COUNTLOW 0xffc03c70 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
219 #define USB_DMA3COUNTHIGH 0xffc03c74 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
226 #define USB_DMA4COUNTLOW 0xffc03c90 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
227 #define USB_DMA4COUNTHIGH 0xffc03c94 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
234 #define USB_DMA5COUNTLOW 0xffc03cb0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
235 #define USB_DMA5COUNTHIGH 0xffc03cb4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
242 #define USB_DMA6COUNTLOW 0xffc03cd0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
243 #define USB_DMA6COUNTHIGH 0xffc03cd4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
250 #define USB_DMA7COUNTLOW 0xffc03cf0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
251 #define USB_DMA7COUNTHIGH 0xffc03cf4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
614 #define PROTOCOL_T 0xc /* transfer type */
623 #define PROTOCOL_R 0xc /* transfer type */
652 #define DIRECTION 0x2 /* direction of DMA transfer */
672 #define DMA_COUNT_HIGH 0xffff /* Upper 16-bits of byte count of DMA transfer for DMA master channel */
676 #define DMA_COUNT_LOW 0xffff /* Lower 16-bits of byte count of DMA transfer for DMA master channel */
/linux-4.1.27/arch/microblaze/lib/
H A Dfastcopy.S23 * Operand3 in Reg r7 - number of bytes to transfer
49 blti r4, a_xfer_end /* if n < 0, less than one word to transfer */
51 /* transfer first 0~3 bytes to get aligned dest address */
60 /* if no bytes left to transfer, transfer the bulk */
72 /* if n < 0, less than one block to transfer */
265 blti r4, a_xfer_end /* if n < 0, less than one word to transfer */
373 blti r4,d_xfer_end /* if n < 0, less than one word to transfer */
375 /* transfer first 0~3 bytes to get aligned dest address */
382 /* if no bytes left to transfer, transfer the bulk */
394 /* if n < 0, less than one block to transfer */
587 blti r4,d_xfer_end /* if n < 0, less than one word to transfer */
/linux-4.1.27/drivers/net/wireless/rsi/
H A Drsi_91x_usb.c37 s32 transfer; rsi_usb_card_write() local
44 &transfer, rsi_usb_card_write()
293 u8 transfer; rsi_usb_write_register_multiple() local
301 transfer = (u8)(min_t(u32, count, 4096)); rsi_usb_write_register_multiple()
302 memcpy(buf, data, transfer); rsi_usb_write_register_multiple()
310 transfer, rsi_usb_write_register_multiple()
317 count -= transfer; rsi_usb_write_register_multiple()
318 data += transfer; rsi_usb_write_register_multiple()
319 addr += transfer; rsi_usb_write_register_multiple()
/linux-4.1.27/arch/blackfin/kernel/
H A Dbfin_dma.c333 * transfer DDR data to L1 SRAM may corrupt data. early_dma_memcpy()
403 * Actually program MDMA0 and wait for the transfer to finish. Disable IRQs
406 * check will make sure we don't clobber any existing transfer.
528 * Do not check arguments before starting the DMA memcpy. Break the transfer
529 * up into two pieces. The first transfer is in multiples of 64k and the
530 * second transfer is the piece smaller than 64k.
551 * Do not check arguments before starting the DMA memcpy. Break the transfer
552 * up into two pieces. The first transfer is in multiples of 64k and the
553 * second transfer is the piece smaller than 64k.
/linux-4.1.27/drivers/ide/
H A Dide-xfer-mode.c21 * @mode: transfer mode
135 * set transfer mode on the device in ->set_pio_mode method... ide_set_pio_mode()
212 * ide_rate_filter - filter transfer mode
216 * Given the available transfer modes this function returns
240 * ide_set_xfer_rate - set transfer rate
H A Dtc86c001.c55 * if a DMA transfer terminates prematurely, the controller leaves the device's
58 * will occur until a DMA transfer has been successfully completed.
60 * We work around this by initiating dummy, zero-length DMA transfer on
85 /* Setup the dummy DMA transfer */ tc86c001_timer_expiry()
89 /* Start the dummy DMA transfer */ tc86c001_timer_expiry()
/linux-4.1.27/arch/sparc/include/asm/
H A Ddma.h18 #define DMA_ADDR 0x04UL /* rw DMA transfer address register 0x04 */
19 #define DMA_COUNT 0x08UL /* rw DMA transfer count register 0x08 */
63 #define DMA_2CLKS 0x00200000 /* Each transfer = 2 clock ticks */
64 #define DMA_3CLKS 0x00400000 /* Each transfer = 3 clock ticks */
94 /* Routines for data transfer buffers. */
/linux-4.1.27/arch/sh/drivers/dma/
H A Ddma-sh.c25 * Define the default configuration for dual address memory-memory transfer.
90 * iterations to complete the transfer.
104 * The transfer end interrupt must read the chcr register to end the
107 * setting up the next transfer.
214 * which will subsequently halt the transfer. sh_dmac_xfer_dma()
H A Ddma-pvr2.c27 printk(KERN_WARNING "DMA: SH DMAC did not complete transfer " pvr2_dma_interrupt()
/linux-4.1.27/Documentation/spi/
H A Dspidev_test.c103 static void transfer(int fd, uint8_t const *tx, uint8_t const *rx, size_t len) transfer() function
157 " -2 --dual dual transfer\n" print_usage()
158 " -4 --quad quad transfer\n"); print_usage()
308 transfer(fd, tx, rx, size); main()
312 transfer(fd, default_tx, default_rx, sizeof(default_tx)); main()
/linux-4.1.27/drivers/misc/sgi-xp/
H A Dxp_sn2.c98 * dst_pa - physical address of the destination of the transfer.
99 * src_pa - physical address of the source of the transfer.
100 * len - number of bytes to transfer from source to destination.
/linux-4.1.27/drivers/staging/rtl8192u/
H A Dr819xU_cmdpkt.h91 /* For endian transfer --> Driver will not the same as
132 /* For endian transfer --> for driver */
145 /* For endian transfer --> for driver */
/linux-4.1.27/drivers/usb/storage/
H A Dtransport.h48 #define USB_STOR_XFER_GOOD 0 /* good transfer */
52 #define USB_STOR_XFER_ERROR 4 /* transfer died in the middle */
65 * return codes. But now the transport and low-level transfer routines
H A Dtransport.c68 * Data transfer routines
148 * transfer buffer has already been mapped. */ usb_stor_msg_common()
258 * Interpret the results of a URB transfer
274 usb_stor_dbg(us, "-- short transfer\n"); interpret_urb_result()
278 usb_stor_dbg(us, "-- transfer complete\n"); interpret_urb_result()
302 /* the transfer was cancelled by abort, disconnect, or timeout */ interpret_urb_result()
304 usb_stor_dbg(us, "-- transfer cancelled\n"); interpret_urb_result()
307 /* short scatter-gather read transfer */ interpret_urb_result()
309 usb_stor_dbg(us, "-- short read transfer\n"); interpret_urb_result()
389 * stalls during the transfer, the halt is automatically cleared.
412 * Transfer a scatter-gather list via bulk transfer
450 /* wait for the completion of the transfer */ usb_stor_bulk_transfer_sglist()
641 * unless the operation involved a data-in transfer. Devices usb_stor_invoke_transport()
676 * A short transfer on a command where we don't expect it usb_stor_invoke_transport()
685 usb_stor_dbg(us, "-- unexpectedly short transfer\n"); usb_stor_invoke_transport()
855 /* Did we transfer less than the minimum amount required? */ usb_stor_invoke_transport()
891 /* Stop the current URB transfer */ usb_stor_stop_transport()
942 /* transfer the data payload for this command, if one exists*/ usb_stor_CB_transport()
949 /* if we stalled the data transfer it means command failed */ usb_stor_CB_transport()
1103 usb_stor_dbg(us, "Bulk command transfer result=%d\n", result); usb_stor_Bulk_transport()
1120 usb_stor_dbg(us, "Bulk data transfer result 0x%x\n", result); usb_stor_Bulk_transport()
1125 * amount requested, the spec requires us to transfer usb_stor_Bulk_transport()
/linux-4.1.27/sound/drivers/
H A Dpcm-indirect2.h2 * Helper functions for indirect PCM data transfer to a simple FIFO in
59 * write) from/to next time (to transfer data to/from HW)
83 * it represents the number of bytes which wait for transfer to the HW
/linux-4.1.27/sound/soc/sh/
H A Dsiu.h80 #define SIU_PERIOD_BYTES_MAX 8192 /* DMA transfer/period size */
81 #define SIU_PERIOD_BYTES_MIN 256 /* DMA transfer/period size */
121 u8 rw_flg; /* transfer status */
/linux-4.1.27/include/linux/amba/
H A Dpl08x.h79 * @get_xfer_signal: request a physical signal to be used for a DMA transfer
81 * of the channel the transfer can be denied by returning less than zero,
84 * running any DMA transfer and multiplexing can be recycled
/linux-4.1.27/drivers/scsi/megaraid/
H A Dmega_common.h55 * @dma_dir : direction of data transfer
56 * @dma_type : transfer with sg list, buffer, or no data transfer
95 #define MRAID_DMA_NONE 0x0000 /* no data transfer for this command */
96 #define MRAID_DMA_WSG 0x0001 /* data transfer using a sg list */
97 #define MRAID_DMA_WBUF 0x0002 /* data transfer using a contiguous buffer */
/linux-4.1.27/drivers/mtd/
H A Dftl.c233 /* Is this a transfer partition? */ build_maps()
244 "transfer units!\n"); build_maps()
329 transfer unit.
369 Prepare_xfer() takes a freshly erased transfer unit and gives
380 /* Look up the transfer unit */ ftl_erase_callback()
419 /* Write the transfer unit header */ prepare_xfer()
453 Copy_erase_unit() takes a full erase block and a transfer unit,
454 copies everything to the transfer unit, then swaps the block
500 /* Write the LogicalEUN for the transfer unit */ copy_erase_unit()
513 /* Copy all data blocks from source unit to transfer unit */ copy_erase_unit()
551 /* Write the BAM to the transfer unit */ copy_erase_unit()
593 reclaim_block() picks a full erase unit and a transfer unit and
597 What's a good way to decide which transfer unit and which erase
598 unit to use? Beats me. My way is to always pick the transfer
615 /* Pick the least erased transfer unit */ reclaim_block()
650 pr_debug("ftl_cs: waiting for transfer " reclaim_block()
657 "suitable transfer units!\n"); reclaim_block()
660 "suitable transfer units!\n"); reclaim_block()
/linux-4.1.27/drivers/media/usb/stk1160/
H A Dstk1160-ac97.c46 * The bit will be cleared when transfer is done. stk1160_write_ac97()
62 * The bit will be cleared when transfer is done. stk1160_read_ac97()
/linux-4.1.27/drivers/usb/gadget/udc/bdc/
H A Dbdc.h228 /* Control transfer BD specific fields */
257 /* One BD can transfer max 65536 bytes */
323 /* Representation of a transfer, one transfer can have multiple bd's */
328 /* this will be the next hw dqp when this transfer completes */
330 /* number of bds in this transfer */
452 * Timer to check if host resumed transfer after bdc sent Func wake
483 /* transfer sr */
/linux-4.1.27/drivers/usb/musb/
H A Dblackfin.h20 * MUSB driver is designed to transfer buffer of N * maxpacket size
22 * transfer in DMA mode 0, so we never transmit a short packet in
/linux-4.1.27/arch/arm/nwfpe/
H A Dfpopcode.h38 CPDT data transfer instructions
49 CPRT joint arithmetic/data transfer instructions
67 uv transfer length (TABLE 1)
93 | w | x | Number of registers to transfer |
197 /* Tests for transfer length */
209 /* Tests for specific data transfer load/store opcodes. */
283 === Definitions for register transfer and comparison instructions
287 #define MASK_CPRT 0x0e000010 /* register transfer opcode */
/linux-4.1.27/include/linux/i2c/
H A Dadp8860.h106 u8 bl_fade_law; /* fade-on/fade-off transfer characteristic */
133 u8 led_fade_law; /* fade-on/fade-off transfer characteristic */
H A Dadp8870.h114 u8 bl_fade_law; /* fade-on/fade-off transfer characteristic */
149 u8 led_fade_law; /* fade-on/fade-off transfer characteristic */
/linux-4.1.27/drivers/cdrom/
H A Dgdrom.c121 int transfer; member in struct:gdrom_unit
552 if (gd.transfer != 1) gdrom_dma_interrupt()
554 gd.transfer = 0; gdrom_dma_interrupt()
633 gd.transfer = 1; gdrom_readdisk_dma()
640 /* start transfer */ gdrom_readdisk_dma()
643 gd.transfer == 0, GDROM_DEFAULT_TIMEOUT); gdrom_readdisk_dma()
644 err = gd.transfer ? -EIO : 0; gdrom_readdisk_dma()
645 gd.transfer = 0; gdrom_readdisk_dma()
716 /* set the default mode for DMA transfer */ gdrom_init_dma_mode()
729 * Bits 14 - 8 start of transfer range in 1 MB blocks OR'ed with 0x80 gdrom_init_dma_mode()
730 * Bits 6 - 0 end of transfer range in 1 MB blocks OR'ed with 0x80 gdrom_init_dma_mode()
/linux-4.1.27/drivers/pnp/pnpacpi/
H A Drsparser.c67 int transfer) dma_flags()
91 switch (transfer) { dma_flags()
104 dev_err(&dev->dev, "invalid DMA transfer type %d\n", transfer); dma_flags()
234 dma->transfer); pnpacpi_allocated_resource()
295 flags = dma_flags(dev, p->type, p->bus_master, p->transfer); pnpacpi_parse_dma_option()
739 dma->transfer = ACPI_TRANSFER_8; pnpacpi_encode_dma()
742 dma->transfer = ACPI_TRANSFER_8_16; pnpacpi_encode_dma()
745 dma->transfer = ACPI_TRANSFER_16; pnpacpi_encode_dma()
753 "type %#x transfer %#x master %d\n", pnpacpi_encode_dma()
754 (int) p->start, dma->type, dma->transfer, dma->bus_master); pnpacpi_encode_dma()
66 dma_flags(struct pnp_dev *dev, int type, int bus_master, int transfer) dma_flags() argument
/linux-4.1.27/drivers/usb/wusbcore/
H A Dwa-xfer.c3 * Data transfer and URB enqueing
29 * the NEP endpoint and a transfer result (struct xfer_result) will
31 * data coming (inbound transfer), schedule a read and handle it.
65 * (which means unused) or when a transfer ends. Reset the
118 struct urb tr_urb; /* transfer request urb. */
126 /* Isoc frame that the current transfer buffer corresponds to. */
156 struct wa_seg **seg; /* transfer segments */
181 * Destroy a transfer structure
278 * reference to the transfer.
308 * Initialize a transfer's ID
333 * If transfer is done, wrap it up and return true
413 * Search for a transfer list ID on the HCD's URB list
501 * Assumes the transfer is referenced and locked and in a submitted
548 * that will fit a in transfer segment.
590 * @returns < 0 on error, transfer segment request size if ok
723 /* populate the isoc section of the transfer request. */ __wa_xfer_setup_hdr0()
767 /* Alereon HWA sends all isoc frames in a single transfer. */ wa_seg_dto_cb()
942 * outbound transfer); otherwise, take a note of the error, mark this
945 * Note we don't access until we are sure that the transfer hasn't
952 * another state. As well, we don't set it if the transfer is not inbound,
1017 * we are about to transfer.
1231 * after the transfer request header in the __wa_xfer_setup_segs()
1300 * Allocates all the stuff needed to submit a transfer
1402 /* submit the transfer request. */ __wa_seg_submit()
1631 * Second part of a URB/transfer enqueuement
1822 * Submit a transfer to the Wire Adapter in a delayed way
1918 * Until a transfer goes successfully through wa_urb_enqueue() it
1927 * If the transfer has gone through setup, we just need to clean it
2032 * about the transfer. If an abort request was sent, wa_urb_dequeue()
2115 "Unknown WA transfer status 0x%02x\n", wa_xfer_status_to_errno()
2130 * If a last segment flag and/or a transfer result error is encountered,
2131 * no other segment transfer results will be returned from the device.
2173 /* Populate the given urb based on the current isoc transfer state. */ __wa_populate_buf_in_urb_isoc()
2229 /* Populate the given urb based on the current transfer state. */ wa_populate_buf_in_urb()
2562 /* OUT transfer or no more IN data, complete it -- */ wa_process_iso_packet_status()
2591 * Note we don't access until we are sure that the transfer hasn't
2738 * Handle an incoming transfer result buffer
2740 * Given a transfer result buffer, it completes the transfer (possibly
2742 * new transfer result read.
2855 * Initialize the DTI URB for reading transfer result notifications and also
2906 * that some endpoint has some transfer result data available. We are
/linux-4.1.27/drivers/net/caif/
H A Dcaif_spi_slave.c51 /* Store previous transfer. */ debugfs_store_prev()
144 /* Start transfer. */ cfspi_xfer()
163 /* Wait for transfer completion. */ cfspi_xfer()
190 /* De-assert transfer signal. */ cfspi_xfer()
/linux-4.1.27/drivers/media/usb/b2c2/
H A Dflexcop-usb.h11 /* transfer parameters */
/linux-4.1.27/drivers/media/usb/gspca/
H A Dgspca.h50 u32 bulk_size; /* buffer size when image transfer by bulk */
53 u8 no_urb_create; /* don't create transfer URBs */
58 u8 bulk; /* image transfer by 0:isoc / 1:bulk */
208 int xfer_ep; /* USB transfer endpoint address */
/linux-4.1.27/drivers/gpu/drm/exynos/
H A Dexynos_drm_crtc.h37 * to trigger to transfer video image at the tearing effect synchronization
/linux-4.1.27/drivers/crypto/qce/
H A Ddma.h19 /* maximum data transfer block size between BAM and CE */
/linux-4.1.27/include/scsi/fc/
H A Dfc_fcp.h105 * FCP_TXRDY IU - transfer ready payload.
177 #define FCP_BIDI_READ_OVER 0x20 /* DL insufficient for full transfer */
179 #define FCP_RESID_UNDER 0x08 /* transfer shorter than expected */
180 #define FCP_RESID_OVER 0x04 /* DL insufficient for full transfer */
/linux-4.1.27/include/uapi/linux/mmc/
H A Dioctl.h52 * to the mmc bus device, an upper data transfer limit of MMC_IOC_MAX_BYTES
/linux-4.1.27/arch/arm64/include/asm/
H A Dcache.h28 * cache before the transfer is done, causing old data to be seen by
/linux-4.1.27/sound/soc/codecs/
H A Dl3.c48 * transfer.
/linux-4.1.27/include/drm/
H A Ddrm_mipi_dsi.h72 * @transfer: transmit a DSI packet
74 * DSI packets transmitted by .transfer() are passed in as mipi_dsi_msg
82 * Note that typically DSI packet transmission is atomic, so the .transfer()
91 ssize_t (*transfer)(struct mipi_dsi_host *host, member in struct:mipi_dsi_host_ops
/linux-4.1.27/drivers/staging/lustre/lustre/llite/
H A Dvvp_page.c241 * Handles page transfer errors at VM level.
312 * ->cpo_completion method. The underlying transfer should be notified vvp_page_completion_write()
313 * and then re-add the page into pending transfer queue. -jay vvp_page_completion_write()
332 * This is called to yank a page from the transfer cache and to send it out as
333 * a part of transfer. This function try-locks the page. If try-lock failed,
335 * but hopefully rare situation, as it usually results in transfer being
338 * \retval 0 success, page can be placed into transfer
/linux-4.1.27/drivers/scsi/pcmcia/
H A Dsym53c500_cs.c81 #define SYNC_MODE 0 /* Synchronous transfer mode */
94 #define TC_LSB 0x00 /* transfer counter lsb */
95 #define TC_MSB 0x01 /* transfer counter msb */
103 #define SYNCPRD 0x06 /* synchronous transfer period */
112 #define TC_HIGH 0x0E /* transfer counter high */
230 outb(0x05, io_port + SYNCPRD); /* Synchronous transfer period */ chip_init()
420 if (int_reg & 0x10) { /* Target requesting info transfer */ SYM53C500_intr()
427 LOAD_DMA_COUNT(port_base, scsi_bufflen(curSC)); /* Max transfer size */ SYM53C500_intr()
439 if (int_reg & 0x10) { /* Target requesting info transfer */
446 LOAD_DMA_COUNT(port_base, scsi_bufflen(curSC)); /* Max transfer size */
/linux-4.1.27/drivers/media/pci/saa7134/
H A Dsaa7134-i2c.c68 NO_ACKN = 10, // no acknowledge after data byte transfer
70 ARB_LOST = 12, // arbitration lost during transfer
82 STOP = 1, // stop condition, no associated byte transfer
83 CONTINUE = 2, // continue with byte transfer
84 START = 3 // start condition with byte transfer
/linux-4.1.27/drivers/ata/
H A Dpata_pxa.c57 * Setup the DMA descriptors. The size is transfer capped at 4k per descriptor,
58 * if the transfer is longer, it is split into multiple chained descriptors.
142 * Execute the DMA transfer.
152 * Wait until the DMA transfer completes, then stop the DMA controller.
167 * DMA transfer so we always have DMA-complete interrupt here.
/linux-4.1.27/drivers/staging/lustre/lustre/include/
H A Dcl_object.h60 * independently, thus achieving high degree of transfer
66 * - cl_req represents a collection of pages for a transfer. cl_req is
74 * RPC, is referred to as "a transfer"
497 * various events changing page state (such as transfer completion, or
569 * PG_locked lock is used to implement both ownership and transfer
572 * transfer.
623 * - [cl_page_state::CPS_PAGEIN] io starts read transfer for
627 * transfer for this page;
636 * Page is being written out, as a part of a transfer. This state is
639 * this state is achieved, transfer completion handler (with either
653 * transfer.
655 * The page leaves cl_page_state::CPS_PAGEOUT state when the transfer
658 * Underlying VM page is locked for the duration of transfer.
664 * Page is being read in, as a part of a transfer. This is quite
670 * Underlying VM page is locked for the duration of transfer.
816 * Requested transfer type.
849 * not owned by other io, and no transfer is going on against
964 * \name transfer
967 * transfer formation and life-cycle.
974 * Transfer operations depend on transfer mode (cl_req_type). To avoid
975 * passing transfer mode to each and every of these methods, and to
984 * Called when a page is submitted for a transfer as a part of
1026 * necessary to start write-out transfer right now, but
1031 * "transfer cache" from which large transfers are then
1045 * Tell transfer engine that only [to, from] part of a page should be
1051 * if all transfer parameters were supplied as arguments to
1086 /** @} transfer */
1672 * State machine transitions. These 3 methods are called to transfer
1686 * is guaranteed, that when the state transfer
1857 * - submit pages for an immediate transfer,
2413 * There are two possible modes of transfer initiation on the client:
2415 * - immediate transfer: this is started when a high level io wants a page
2419 * as a part of memory cleansing. Immediate transfer can be both
2422 * - opportunistic transfer (cl_req_type::CRT_WRITE only), that happens
2423 * when io wants to transfer a page to the server some time later, when
2427 * In any case, transfer takes place in the form of a cl_req, which is a
2430 * Pages queued for an opportunistic transfer are cached until it is decided
2437 * For the immediate transfer io submits a cl_page_list, that req-formation
2458 * transfer right now.
2463 * submitting cl_page_list, and queuing a page for the opportunistic transfer)
2471 * Per-transfer attributes.
2485 * Concurrency: transfer formation engine synchronizes calls to all transfer
2490 * Invoked top-to-bottom by cl_req_prep() when transfer formation is
2514 * transfer completed. Has to free all state allocated by
2522 * A per-object state that (potentially multi-object) transfer request keeps.
2549 * deny it completely. This is to support things like SNS that have transfer
2552 * On transfer completion (or transfer timeout, or failure to initiate the
2553 * transfer of an allocated req), cl_req_operations::cro_completion() method
2845 * \name transfer
2847 * Functions dealing with the preparation of a page for a transfer, and
2848 * tracking transfer state.
2865 /** @} transfer */
3192 * Anchor for synchronous transfer. This is allocated on a stack by thread
3193 * doing synchronous transfer, and a pointer to this structure is set up in
3194 * every page submitted for transfer. Transfer completion routine updates
3195 * anchor and wakes up waiting thread when transfer is complete.
3204 /** completion to be signaled when transfer is complete. */
/linux-4.1.27/drivers/usb/core/
H A Durb.c87 * Note: The transfer buffer associated with the urb is not freed unless the
88 * URB_FREE_BUFFER transfer flag is set.
189 * usb_submit_urb - issue an asynchronous transfer request for an endpoint
194 * This submits a transfer request, and transfers control of the URB
205 * the particular kind of transfer, although they will not initialize
206 * any transfer flags.
217 * The exceptions relate to periodic transfer scheduling. For both
219 * urb->interval is modified to reflect the actual transfer period used
224 * Not all isochronous transfer scheduling policies will work, but most
262 * As of Linux 2.6, all USB endpoint transfer queues support depths greater
265 * after faults (transfer errors or cancellation).
480 * Force periodic transfer intervals to be legal values that are usb_submit_urb()
549 * usb_unlink_urb - abort/cancel a transfer request for an endpoint
614 * and clean them up reliably after any sort of aborted transfer by
618 * is quite likely that the status stage of the transfer will not take
634 * usb_kill_urb - cancel a transfer request and wait for it to finish
675 * usb_poison_urb - reliably kill a transfer and prevent further use of an URB
747 * usb_kill_anchored_urbs - cancel transfer requests en masse
830 * usb_unlink_anchored_urbs - asynchronously cancel transfer requests en masse
/linux-4.1.27/drivers/gpu/drm/
H A Ddrm_dp_helper.c170 * structure, which is passed into a driver's .transfer() implementation.
196 err = aux->transfer(aux, &msg); drm_dp_dpcd_access()
235 * function returns -EPROTO. Errors from the underlying AUX channel transfer
257 * function returns -EPROTO. Errors from the underlying AUX channel transfer
428 * aux->transfer function does not modify anything in the msg other than the
445 ret = aux->transfer(aux, msg); drm_dp_i2c_do_msg()
491 * can assume the transfer was successful. drm_dp_i2c_do_msg()
519 * Returns an error code on failure, or a recommended transfer size on success.
552 "Number of bytes to transfer in a single I2C over DP AUX CH message, (1-16, default 16)");

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