Searched refs:tiling_flags (Results 1 - 18 of 18) sorted by relevance

/linux-4.1.27/drivers/gpu/drm/radeon/
H A Dradeon_object.c575 lobj->tiling_flags = bo->tiling_flags; list_for_each_entry()
580 lobj->tiling_flags = lobj->robj->tiling_flags;
596 if (!bo->tiling_flags) radeon_bo_get_surface_reg()
635 radeon_set_surface_reg(rdev, i, bo->tiling_flags, bo->pitch, radeon_bo_get_surface_reg()
657 uint32_t tiling_flags, uint32_t pitch) radeon_bo_set_tiling_flags()
665 bankw = (tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK; radeon_bo_set_tiling_flags()
666 bankh = (tiling_flags >> RADEON_TILING_EG_BANKH_SHIFT) & RADEON_TILING_EG_BANKH_MASK; radeon_bo_set_tiling_flags()
667 mtaspect = (tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK; radeon_bo_set_tiling_flags()
668 tilesplit = (tiling_flags >> RADEON_TILING_EG_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_TILE_SPLIT_MASK; radeon_bo_set_tiling_flags()
669 stilesplit = (tiling_flags >> RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK; radeon_bo_set_tiling_flags()
710 bo->tiling_flags = tiling_flags; radeon_bo_set_tiling_flags()
717 uint32_t *tiling_flags, radeon_bo_get_tiling_flags()
722 if (tiling_flags) radeon_bo_get_tiling_flags()
723 *tiling_flags = bo->tiling_flags; radeon_bo_get_tiling_flags()
734 if (!(bo->tiling_flags & RADEON_TILING_SURFACE)) radeon_bo_check_tiling()
656 radeon_bo_set_tiling_flags(struct radeon_bo *bo, uint32_t tiling_flags, uint32_t pitch) radeon_bo_set_tiling_flags() argument
716 radeon_bo_get_tiling_flags(struct radeon_bo *bo, uint32_t *tiling_flags, uint32_t *pitch) radeon_bo_get_tiling_flags() argument
H A Dradeon_fb.c142 u32 tiling_flags = 0; radeonfb_create_pinned_object() local
169 tiling_flags = RADEON_TILING_MACRO; radeonfb_create_pinned_object()
174 tiling_flags |= RADEON_TILING_SWAP_32BIT; radeonfb_create_pinned_object()
177 tiling_flags |= RADEON_TILING_SWAP_16BIT; radeonfb_create_pinned_object()
183 if (tiling_flags) { radeonfb_create_pinned_object()
185 tiling_flags | RADEON_TILING_SURFACE, radeonfb_create_pinned_object()
H A Dr200.c221 if (reloc->tiling_flags & RADEON_TILING_MACRO) r200_packet0_check()
223 if (reloc->tiling_flags & RADEON_TILING_MICRO) r200_packet0_check()
293 if (reloc->tiling_flags & RADEON_TILING_MACRO) r200_packet0_check()
295 if (reloc->tiling_flags & RADEON_TILING_MICRO) r200_packet0_check()
H A Dr300.c695 if (reloc->tiling_flags & RADEON_TILING_MACRO) r300_packet0_check()
697 if (reloc->tiling_flags & RADEON_TILING_MICRO) r300_packet0_check()
699 else if (reloc->tiling_flags & RADEON_TILING_MICRO_SQUARE) r300_packet0_check()
764 if (reloc->tiling_flags & RADEON_TILING_MACRO) r300_packet0_check()
766 if (reloc->tiling_flags & RADEON_TILING_MICRO) r300_packet0_check()
768 else if (reloc->tiling_flags & RADEON_TILING_MICRO_SQUARE) r300_packet0_check()
849 if (reloc->tiling_flags & RADEON_TILING_MACRO) r300_packet0_check()
851 if (reloc->tiling_flags & RADEON_TILING_MICRO) r300_packet0_check()
853 else if (reloc->tiling_flags & RADEON_TILING_MICRO_SQUARE) r300_packet0_check()
H A Dradeon_object.h147 u32 tiling_flags, u32 pitch);
149 u32 *tiling_flags, u32 *pitch);
H A Devergreen_cs.c89 static u32 evergreen_cs_get_aray_mode(u32 tiling_flags) evergreen_cs_get_aray_mode() argument
91 if (tiling_flags & RADEON_TILING_MACRO) evergreen_cs_get_aray_mode()
93 else if (tiling_flags & RADEON_TILING_MICRO) evergreen_cs_get_aray_mode()
1200 ib[idx] |= Z_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags)); evergreen_cs_check_reg()
1201 track->db_z_info |= Z_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags)); evergreen_cs_check_reg()
1202 if (reloc->tiling_flags & RADEON_TILING_MACRO) { evergreen_cs_check_reg()
1205 evergreen_tiling_fields(reloc->tiling_flags, evergreen_cs_check_reg()
1385 ib[idx] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags)); evergreen_cs_check_reg()
1386 track->cb_color_info[tmp] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags)); evergreen_cs_check_reg()
1403 ib[idx] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags)); evergreen_cs_check_reg()
1404 track->cb_color_info[tmp] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags)); evergreen_cs_check_reg()
1465 if (reloc->tiling_flags & RADEON_TILING_MACRO) { evergreen_cs_check_reg()
1468 evergreen_tiling_fields(reloc->tiling_flags, evergreen_cs_check_reg()
1493 if (reloc->tiling_flags & RADEON_TILING_MACRO) { evergreen_cs_check_reg()
1496 evergreen_tiling_fields(reloc->tiling_flags, evergreen_cs_check_reg()
2375 TEX_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags)); evergreen_packet3_check()
2376 if (reloc->tiling_flags & RADEON_TILING_MACRO) { evergreen_packet3_check()
2379 evergreen_tiling_fields(reloc->tiling_flags, evergreen_packet3_check()
H A Datombios_crtc.c1147 uint32_t fb_format, fb_pitch_pixels, tiling_flags; dce4_crtc_do_set_base() local
1188 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL); dce4_crtc_do_set_base()
1261 if (tiling_flags & RADEON_TILING_MACRO) { dce4_crtc_do_set_base()
1262 evergreen_tiling_fields(tiling_flags, &bankw, &bankh, &mtaspect, &tile_split); dce4_crtc_do_set_base()
1334 } else if (tiling_flags & RADEON_TILING_MICRO) dce4_crtc_do_set_base()
1464 uint32_t fb_format, fb_pitch_pixels, tiling_flags; avivo_crtc_do_set_base() local
1503 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL); avivo_crtc_do_set_base()
1564 if (tiling_flags & RADEON_TILING_MACRO) avivo_crtc_do_set_base()
1566 else if (tiling_flags & RADEON_TILING_MICRO) avivo_crtc_do_set_base()
1569 if (tiling_flags & RADEON_TILING_MACRO) avivo_crtc_do_set_base()
1572 if (tiling_flags & RADEON_TILING_MICRO) avivo_crtc_do_set_base()
H A Dr600_cs.c1044 if (reloc->tiling_flags & RADEON_TILING_MACRO) { r600_cs_check_reg()
1143 if (reloc->tiling_flags & RADEON_TILING_MACRO) { r600_cs_check_reg()
1146 } else if (reloc->tiling_flags & RADEON_TILING_MICRO) { r600_cs_check_reg()
1474 u32 tiling_flags) r600_check_texture_resource()
1496 if (tiling_flags & RADEON_TILING_MACRO) r600_check_texture_resource()
1498 else if (tiling_flags & RADEON_TILING_MICRO) r600_check_texture_resource()
1967 if (reloc->tiling_flags & RADEON_TILING_MACRO) r600_packet3_check()
1969 else if (reloc->tiling_flags & RADEON_TILING_MICRO) r600_packet3_check()
1985 reloc->tiling_flags); r600_packet3_check()
1469 r600_check_texture_resource(struct radeon_cs_parser *p, u32 idx, struct radeon_bo *texture, struct radeon_bo *mipmap, u64 base_offset, u64 mip_offset, u32 tiling_flags) r600_check_texture_resource() argument
H A Dradeon_legacy_crtc.c381 uint32_t tiling_flags; radeon_crtc_do_set_base() local
463 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL); radeon_crtc_do_set_base()
465 if (tiling_flags & RADEON_TILING_MICRO) radeon_crtc_do_set_base()
483 if (tiling_flags & RADEON_TILING_MACRO) { radeon_crtc_do_set_base()
499 if (tiling_flags & RADEON_TILING_MACRO) { radeon_crtc_do_set_base()
H A Dr100.c1283 if (reloc->tiling_flags & RADEON_TILING_MACRO) r100_reloc_pitch_offset()
1285 if (reloc->tiling_flags & RADEON_TILING_MICRO) { r100_reloc_pitch_offset()
1625 if (reloc->tiling_flags & RADEON_TILING_MACRO) r100_packet0_check()
1627 if (reloc->tiling_flags & RADEON_TILING_MICRO) r100_packet0_check()
1706 if (reloc->tiling_flags & RADEON_TILING_MACRO) r100_packet0_check()
1708 if (reloc->tiling_flags & RADEON_TILING_MICRO) r100_packet0_check()
3096 uint32_t tiling_flags, uint32_t pitch, r100_set_surface_reg()
3103 if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO)) r100_set_surface_reg()
3106 if (tiling_flags & RADEON_TILING_MACRO) r100_set_surface_reg()
3109 if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO)) r100_set_surface_reg()
3113 if (tiling_flags & (RADEON_TILING_MACRO)) r100_set_surface_reg()
3115 if (tiling_flags & RADEON_TILING_MICRO) r100_set_surface_reg()
3118 if (tiling_flags & RADEON_TILING_MACRO) r100_set_surface_reg()
3120 if (tiling_flags & RADEON_TILING_MICRO) r100_set_surface_reg()
3124 if (tiling_flags & RADEON_TILING_SWAP_16BIT) r100_set_surface_reg()
3126 if (tiling_flags & RADEON_TILING_SWAP_32BIT) r100_set_surface_reg()
3095 r100_set_surface_reg(struct radeon_device *rdev, int reg, uint32_t tiling_flags, uint32_t pitch, uint32_t offset, uint32_t obj_size) r100_set_surface_reg() argument
H A Dradeon_gem.c497 r = radeon_bo_set_tiling_flags(robj, args->tiling_flags, args->pitch); radeon_gem_set_tiling_ioctl()
518 radeon_bo_get_tiling_flags(rbo, &args->tiling_flags, &args->pitch); radeon_gem_get_tiling_ioctl()
H A Dradeon_vm.c146 list[0].tiling_flags = 0; radeon_vm_get_bos()
158 list[idx].tiling_flags = 0; radeon_vm_get_bos()
H A Dradeon_display.c460 uint32_t tiling_flags, pitch_pixels; radeon_crtc_page_flip() local
507 radeon_bo_get_tiling_flags(new_rbo, &tiling_flags, NULL); radeon_crtc_page_flip()
515 if (tiling_flags & RADEON_TILING_MACRO) { radeon_crtc_page_flip()
H A Dradeon.h347 extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
463 uint32_t tiling_flags; member in struct:radeon_bo_list
496 u32 tiling_flags; member in struct:radeon_bo
1940 uint32_t tiling_flags, uint32_t pitch,
H A Dradeon_asic.h91 uint32_t tiling_flags, uint32_t pitch,
339 uint32_t tiling_flags, uint32_t pitch,
H A Devergreen.c1037 void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw, evergreen_tiling_fields() argument
1041 *bankw = (tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK; evergreen_tiling_fields()
1042 *bankh = (tiling_flags >> RADEON_TILING_EG_BANKH_SHIFT) & RADEON_TILING_EG_BANKH_MASK; evergreen_tiling_fields()
1043 *mtaspect = (tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK; evergreen_tiling_fields()
1044 *tile_split = (tiling_flags >> RADEON_TILING_EG_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_TILE_SPLIT_MASK; evergreen_tiling_fields()
H A Dr600.c2979 uint32_t tiling_flags, uint32_t pitch, r600_set_surface_reg()
2978 r600_set_surface_reg(struct radeon_device *rdev, int reg, uint32_t tiling_flags, uint32_t pitch, uint32_t offset, uint32_t obj_size) r600_set_surface_reg() argument
/linux-4.1.27/include/uapi/drm/
H A Dradeon_drm.h854 uint32_t tiling_flags; member in struct:drm_radeon_gem_set_tiling
860 uint32_t tiling_flags; member in struct:drm_radeon_gem_get_tiling

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