Searched refs:sirfsoc_timer_base (Results 1 - 2 of 2) sorted by relevance

/linux-4.1.27/drivers/clocksource/
H A Dtimer-prima2.c57 static void __iomem *sirfsoc_timer_base; variable
64 WARN_ON(!(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_STATUS) & sirfsoc_timer_interrupt()
68 writel_relaxed(BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_STATUS); sirfsoc_timer_interrupt()
82 sirfsoc_timer_base + SIRFSOC_TIMER_LATCH); sirfsoc_timer_read()
83 cycles = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_LATCHED_HI); sirfsoc_timer_read()
85 readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_LATCHED_LO); sirfsoc_timer_read()
96 sirfsoc_timer_base + SIRFSOC_TIMER_LATCH); sirfsoc_timer_set_next_event()
97 now = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_LATCHED_LO); sirfsoc_timer_set_next_event()
99 writel_relaxed(next, sirfsoc_timer_base + SIRFSOC_TIMER_MATCH_0); sirfsoc_timer_set_next_event()
101 sirfsoc_timer_base + SIRFSOC_TIMER_LATCH); sirfsoc_timer_set_next_event()
102 now = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_LATCHED_LO); sirfsoc_timer_set_next_event()
110 u32 val = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_INT_EN); sirfsoc_timer_set_mode()
117 sirfsoc_timer_base + SIRFSOC_TIMER_INT_EN); sirfsoc_timer_set_mode()
121 sirfsoc_timer_base + SIRFSOC_TIMER_INT_EN); sirfsoc_timer_set_mode()
134 sirfsoc_timer_base + SIRFSOC_TIMER_LATCH); sirfsoc_clocksource_suspend()
138 readl_relaxed(sirfsoc_timer_base + sirfsoc_clocksource_suspend()
148 sirfsoc_timer_base + sirfsoc_timer_reg_list[i]); sirfsoc_clocksource_resume()
151 sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_LO); sirfsoc_clocksource_resume()
153 sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_HI); sirfsoc_clocksource_resume()
211 sirfsoc_timer_base = of_iomap(np, 0); sirfsoc_prima2_timer_init()
212 if (!sirfsoc_timer_base) sirfsoc_prima2_timer_init()
218 sirfsoc_timer_base + SIRFSOC_TIMER_DIV); sirfsoc_prima2_timer_init()
219 writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_LO); sirfsoc_prima2_timer_init()
220 writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_HI); sirfsoc_prima2_timer_init()
221 writel_relaxed(BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_STATUS); sirfsoc_prima2_timer_init()
H A Dtimer-atlas7.c54 static void __iomem *sirfsoc_timer_base; variable
59 writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx) & ~0x7, sirfsoc_timer_count_disable()
60 sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx); sirfsoc_timer_count_disable()
66 writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx) | 0x3, sirfsoc_timer_count_enable()
67 sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx); sirfsoc_timer_count_enable()
77 writel_relaxed(BIT(cpu), sirfsoc_timer_base + SIRFSOC_TIMER_INTR_STATUS); sirfsoc_timer_interrupt()
92 writel_relaxed((readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL) | sirfsoc_timer_read()
93 BIT(0)) & ~BIT(1), sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL); sirfsoc_timer_read()
95 cycles = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_RLATCHED_HI); sirfsoc_timer_read()
96 cycles = (cycles << 32) | readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_RLATCHED_LO); sirfsoc_timer_read()
109 writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_0 + sirfsoc_timer_set_next_event()
111 writel_relaxed(delta, sirfsoc_timer_base + SIRFSOC_TIMER_MATCH_0 + sirfsoc_timer_set_next_event()
139 sirfsoc_timer_reg_val[i] = readl_relaxed(sirfsoc_timer_base + sirfsoc_timer_reg_list[i]); sirfsoc_clocksource_suspend()
147 writel_relaxed(sirfsoc_timer_reg_val[i], sirfsoc_timer_base + sirfsoc_timer_reg_list[i]); sirfsoc_clocksource_resume()
150 sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_LOAD_LO); sirfsoc_clocksource_resume()
152 sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_LOAD_HI); sirfsoc_clocksource_resume()
154 writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL) | sirfsoc_clocksource_resume()
155 BIT(1) | BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL); sirfsoc_clocksource_resume()
270 writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL); sirfsoc_atlas7_timer_init()
271 writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL); sirfsoc_atlas7_timer_init()
272 writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_1_CTRL); sirfsoc_atlas7_timer_init()
275 writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_LOAD_LO); sirfsoc_atlas7_timer_init()
276 writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_LOAD_HI); sirfsoc_atlas7_timer_init()
277 writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL) | sirfsoc_atlas7_timer_init()
278 BIT(1) | BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL); sirfsoc_atlas7_timer_init()
279 writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_0); sirfsoc_atlas7_timer_init()
280 writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_1); sirfsoc_atlas7_timer_init()
283 writel_relaxed(0xFFFF, sirfsoc_timer_base + SIRFSOC_TIMER_INTR_STATUS); sirfsoc_atlas7_timer_init()
292 sirfsoc_timer_base = of_iomap(np, 0); sirfsoc_of_timer_init()
293 if (!sirfsoc_timer_base) sirfsoc_of_timer_init()

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