Searched refs:pipe_bpp (Results 1 - 14 of 14) sorted by relevance

/linux-4.1.27/drivers/gpu/drm/i915/
H A Dintel_dsi_pll.c305 static void assert_bpp_mismatch(int pixel_format, int pipe_bpp) assert_bpp_mismatch() argument
323 WARN(bpp != pipe_bpp, assert_bpp_mismatch()
325 bpp, pipe_bpp); assert_bpp_mismatch()
328 u32 vlv_get_dsi_pclk(struct intel_encoder *encoder, int pipe_bpp) vlv_get_dsi_pclk() argument
378 /* pixel_format and pipe_bpp should agree */ vlv_get_dsi_pclk()
379 assert_bpp_mismatch(intel_dsi->pixel_format, pipe_bpp); vlv_get_dsi_pclk()
381 pclk = DIV_ROUND_CLOSEST(dsi_clock * intel_dsi->lane_count, pipe_bpp); vlv_get_dsi_pclk()
H A Dintel_dp_mst.c68 pipe_config->pipe_bpp = 24; intel_dp_mst_compute_config()
261 pipe_config->pipe_bpp = 18; intel_dp_mst_enc_get_config()
264 pipe_config->pipe_bpp = 24; intel_dp_mst_enc_get_config()
267 pipe_config->pipe_bpp = 30; intel_dp_mst_enc_get_config()
270 pipe_config->pipe_bpp = 36; intel_dp_mst_enc_get_config()
H A Dintel_dsi.h126 extern u32 vlv_get_dsi_pclk(struct intel_encoder *encoder, int pipe_bpp);
H A Dintel_ddi.c1247 switch (intel_crtc->config->pipe_bpp) { intel_ddi_set_pipe_settings()
1299 switch (intel_crtc->config->pipe_bpp) { intel_ddi_enable_transcoder_func()
2106 pipe_config->pipe_bpp = 18; intel_ddi_get_config()
2109 pipe_config->pipe_bpp = 24; intel_ddi_get_config()
2112 pipe_config->pipe_bpp = 30; intel_ddi_get_config()
2115 pipe_config->pipe_bpp = 36; intel_ddi_get_config()
2148 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) { intel_ddi_get_config()
2163 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp); intel_ddi_get_config()
2164 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp; intel_ddi_get_config()
H A Dintel_lvds.c194 if (crtc->config->dither && crtc->config->pipe_bpp == 18) intel_pre_enable_lvds()
303 if (lvds_bpp != pipe_config->pipe_bpp && !pipe_config->bw_constrained) { intel_lvds_compute_config()
305 pipe_config->pipe_bpp, lvds_bpp); intel_lvds_compute_config()
306 pipe_config->pipe_bpp = lvds_bpp; intel_lvds_compute_config()
H A Dintel_crt.c316 if (pipe_config->bw_constrained && pipe_config->pipe_bpp < 24) { intel_crt_compute_config()
321 pipe_config->pipe_bpp = 24; intel_crt_compute_config()
H A Dintel_dsi.c635 pclk = vlv_get_dsi_pclk(encoder, pipe_config->pipe_bpp); intel_dsi_get_config()
697 unsigned int bpp = intel_crtc->config->pipe_bpp; set_dsi_timings()
754 unsigned int bpp = intel_crtc->config->pipe_bpp; intel_dsi_prepare()
H A Dintel_display.c5782 pipe_config->pipe_bpp); ironlake_fdi_compute_config()
5786 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock, ironlake_fdi_compute_config()
5791 if (!setup_ok && pipe_config->pipe_bpp > 6*3) { ironlake_fdi_compute_config()
5792 pipe_config->pipe_bpp -= 2*3; ironlake_fdi_compute_config()
5794 pipe_config->pipe_bpp); ironlake_fdi_compute_config()
5812 pipe_config->pipe_bpp <= 24; hsw_compute_ips_config()
5861 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) { intel_crtc_compute_config()
5862 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */ intel_crtc_compute_config()
5863 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) { intel_crtc_compute_config()
5866 pipe_config->pipe_bpp = 8*3; intel_crtc_compute_config()
6736 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30) i9xx_set_pipeconf()
6740 switch (intel_crtc->config->pipe_bpp) { i9xx_set_pipeconf()
7059 pipe_config->pipe_bpp = 18; i9xx_get_pipe_config()
7062 pipe_config->pipe_bpp = 24; i9xx_get_pipe_config()
7065 pipe_config->pipe_bpp = 30; i9xx_get_pipe_config()
7527 switch (intel_crtc->config->pipe_bpp) { ironlake_set_pipeconf()
7652 switch (intel_crtc->config->pipe_bpp) { haswell_set_pipeconf()
8189 pipe_config->pipe_bpp = 18; ironlake_get_pipe_config()
8192 pipe_config->pipe_bpp = 24; ironlake_get_pipe_config()
8195 pipe_config->pipe_bpp = 30; ironlake_get_pipe_config()
8198 pipe_config->pipe_bpp = 36; ironlake_get_pipe_config()
10376 int bpp = pipe_config->pipe_bpp; connected_sink_compute_bpp()
10387 pipe_config->pipe_bpp = connector->base.display_info.bpc*3; connected_sink_compute_bpp()
10403 pipe_config->pipe_bpp = clamp_bpp; connected_sink_compute_bpp()
10454 pipe_config->pipe_bpp = bpp; compute_baseline_pipe_bpp()
10493 pipe_config->pipe_bpp, pipe_config->dither); intel_dump_pipe_config()
10683 /* Compute a starting value for pipe_config->pipe_bpp taking the source intel_modeset_pipe_config()
10757 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp; intel_modeset_pipe_config()
10759 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither); intel_modeset_pipe_config()
11117 PIPE_CONF_CHECK_I(pipe_bpp); intel_pipe_config_compare()
H A Dintel_hdmi.c715 if (crtc->config->pipe_bpp > 24) intel_hdmi_prepare()
1032 if (pipe_config->pipe_bpp > 8*3 && pipe_config->has_hdmi_sink && intel_hdmi_compute_config()
1047 pipe_config->pipe_bpp = desired_bpp; intel_hdmi_compute_config()
H A Dintel_dp.c1383 bpp = pipe_config->pipe_bpp; intel_dp_compute_config()
1452 pipe_config->pipe_bpp = bpp; intel_dp_compute_config()
2275 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) { intel_dp_get_config()
2290 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp); intel_dp_get_config()
2291 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp; intel_dp_get_config()
H A Dintel_panel.c372 if (INTEL_INFO(dev)->gen < 4 && pipe_config->pipe_bpp == 18) intel_gmch_panel_fitting()
H A Dintel_drv.h349 int pipe_bpp; member in struct:intel_crtc_state
H A Dintel_tv.c929 pipe_config->pipe_bpp = 8*3; intel_tv_compute_config()
H A Dintel_sdvo.c1123 pipe_config->pipe_bpp = 8*3; intel_sdvo_compute_config()

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